Kabushiki Kaisha Toshiba

Masao Kuriyama

Hidetoshi Saito

Shigeru Atsumi

Tadayuki Taura

Yasuhiko Honda

Hironori Banba

Hideo Kato

Tokumasa Hara

Akira Umezawa

Takafumi Ikeda

Tatsuya Hiramatsu

Toru Tanzawa

Nobuaki Otsuka

Tooru Tanzawa

Seiichi Mori

Sumio Tanaka

Seiji Yamada

Junichi Miyamoto

Tadashi Miyakawa

Nobuaki Ohtsuka

Yoshinori Takano

Takeshi Miyaba

A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

Nonvolatile semiconductor memory device which stores multivalue data

A semiconductor device includes a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks. The semiconductor device further includes a first power supply line which is provided commonly for said plurality of cores and which provides a data reading power supply potential; a second power supply line which is provided commonly for said plurality of cores and which provides a data writing or erasing power supply potential; and a power supply line switching circuit which is provided for each of said plurality of cores and which selectively connects a corresponding one of said plurality of cores to said first power supply line or said second power supply line in accordance with whether said corresponding one of said plurality of cores is in a data read mode or a data write or erase mode.

Semiconductor device that enables simultaneous read and write/read operation

A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.

Semiconductor intergrated circuit device with a main cell array and a fuse cell array whose word lines and bit lines are extended in the same directions

A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT=EVT+(OEVT&#x2212;EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVTand is lower than OEVT. The erase verify threshold values EVTand EVTare switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT. On the other hand, during the normal operation, the erase verify threshold value is set at EVT

Nonvolatile semiconductor memory

A semiconductor integrated circuit device includes fuse cells arranged at a fuse cell array, a fuse cell data program and erase circuit, a fuse cell data control circuit, and fuse data latch circuits. The fuse cells include erasable and programmable nonvolatile memory cells. The fuse cell data program and erase circuit programs fuse data to the memory cells and erases the fuse data from the memory cells. The fuse cell data control circuit controls read out timing of the fuse data stored in the memory cells based on a signal generated upon detection of power-on. The fuse data latch circuits latch the fuse data read out from the memory cells.

Semiconductor integrated circuit device with erasable and programmable fuse memory

A nonvolatile semiconductor memory device with a plurality of read modes switchably built therein is provided. This nonvolatile semiconductor memory device is the one that has a memory cell array in which electrically rewritable nonvolatile memory cells are laid out and a read circuit which performs data readout of the memory cell array. The nonvolatile semiconductor memory device has a first read mode and a second read mode. The first read mode is for reading data by means of parallel data transfer of the same bit number when sending data from the memory cell array through the read circuit up to more than one external terminal. The second read mode is for performing parallel data transfer of a greater bit number than that of the first read mode when sending data from the memory cell array to the read circuit while performing data transfer of a smaller bit number than the bit number when sending data from the read circuit up to the external terminal.

Nonvolatile semiconductor memory device with first and second read modes

A memory cell array has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part.

A semiconductor memory device, which allows concurrent execution of a write/erase operation and a read operation, is provided for each core with a core busy output circuit which has a function of, at the start, end, suspending or resuming of a write/erase operation, setting the sequence in which a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are set or reset so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.

Nonvolatile semiconductor memory device capable of concurrently and reliably writing/erasing and reading memory cores

A potential generating circuit generates two types of erase verify threshold values EVT and EVT . These values satisfy the relationship of EVT &equals;EVT &plus;(OEVT&minus;EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT , the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT and is lower than OEVT. The erase verify threshold values EVT and EVT are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT . On the other hand, during the normal operation, the erase verify threshold value is set at EVT

A semiconductor integrated circuit device includes a nonvolatile memory cell, a source of the cell receiving a ground potential, and a gate of the cell receiving a first control signal; a transistor, a source of the transistor receiving a drain potential of the cell, and a gate of the transistor receiving a second control signal; and a controller. The controller receives a third control signal generated upon detection of power-on and outputs the first and second control signals. A potential of the first control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a first period of time, and a potential of the second control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a second period of time.

Semiconductor integrated circuit device with operation/function setting information memory

A nonvolatile semiconductor memory includes a memory cell array and a redundant cell array, and while a data write operation or a data erase operation is carried out in one of banks in the memory cell array, a data read operation can be carried out in the other banks. The redundant cell array has one or more spare blocks and is provided independently of the banks to relieve a defective memory cell of the memory cell array by substituting the spare block for a defective memory block in any of the blocks. The memory block is active when an access block address to be accessed in the memory cell array in the data write or erase operation or the data read operation does not coincide with the defective block address in the defective address storing circuit, whereas the spare block is active when the access block address coincides with the defective block address in the defective address storing circuit.

Growing community of inventors

Fujisawa, Japan

Masao Kuriyama