Nippon Gakki Seizo Kabushiki Kaisha

Masao Kosugi

Takashi Yoshida

Takeshi Matsuyama

Takashi Ogata

On a common semiconductor wafer constituted by a PN-lamination are formed a number of semiconductor device units. Recessed grooves are formed into this wafer by an etching technique at such sites as one corresponding to the boundaries of the respective adjacent semiconductor device units. To protect the PN-junctions of the wafer exposed on the etched grooves, these surfaces are coated with a thermo-setting resin. Thereafter, the semiconductor wafer is severed apart at the respective recessed grooves into respective individual chips of semiconductor devices.

Process of manufacturing semiconductor devices

A field effect transistor having unsaturated characteristics comprising a plurality of current channels consisting of a semiconductor material of an impurity concentration between 1 .times. 10.sup.13 to 1 .times. 10.sup.15 atoms/c.c., each current channel having a minimum diameter between 2 and 15 .mu.m so that the depletion layer growing from the gate junction nearly but not perfectly closes the current channel at zero gate bias. This junction type field effect transistor provides unsaturated and well aligned parallel characteristic curves and reduces power loss as compared to conventional unsaturated type vertical field effect transistors.

Growing community of inventors

Hamakita, Japan

Masao Kosugi