Sandisk Technologies Inc.

Masanori Tsutsumi

Shinsuke Yada

Raghuveer S Makala

Tatsuya Hinoue

Seiji Shimabukuro

Naohiro Hosoda

Yanli Zhang

Akio Nishida

Hiroyuki Ogawa

Genta Mizuno

Yusuke Mukae

Sayako Nagamine

Rahul Sharangpani

Senaka Kanakamedala

Michiaki Sano

Naoki Takeguchi

Mitsuteru Mushiga

Shigehisa Inoue

Ryo Nakamura

Yu Ueda

Johann Alsmeier

Fei Zhou

Kiyohiko Sakakibara

Kensuke Yamaguchi

Kota Funayama

Teruo Okina

Yuji Fukano

Kazuki Isozumi

Ryoichi Ehara

Youko Furihata

Shuichi Hamaguchi

Masaaki Higashitani

Christopher John Petti

James K Kai

George Matamis

Jayavel Pachamuthu

Tong Zhang

Adarsh Rajashekhar

Masatoshi Nishikawa

Wei Zhao

Zhixin Cui

Sateesh Koka

Ramy Nashed Bassely Said

Zhenyu Lu

Somesh Peri

Takaaki Iwai

Kengo Kajiwara

Tadashi Nakamura

Tomohiro Kubo

Ryoichi Honma

Ryousuke Itou

Junichi Ariyoshi

Shigehiro Fujino

Yusuke Ikawa

Keerti Shukla

Hiroshi Sasaki

Yuki Kasai

Shuji Minagawa

Masato Miyamoto

Eisuke Takii

Motoki Kawasaki

Keisuke Shigemura

Jo Sato

Junji Oh

Hajime Kimura

Hisaya Sakai

Manabu Kakazu

Naoki Ihata

Hiromasa Susuki

A bonded assembly includes a first memory die and a logic die. The first memory die includes a first alternating stack of first insulating layers and first electrically conductive layers, first memory opening fill structures, a first stepped dielectric material portion, and first column-shaped conductive via structures including a respective conductive shaft portion vertically extending through a respective subset of the first electrically conductive layers, a respective conductive base portion, and a respective conductive capital portion contacting a horizontal surface of a respective one of the first electrically conductive layers. The logic die includes logic-side bonding pads that are bonded to the first column-shaped conductive via structures.

Bonded assembly containing conductive via structures extending through word lines in a staircase region and methods for making the same

A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.

Three-dimensional memory device and method of making thereof using double pitch word line formation

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a first metal oxide blocking dielectric layer, and a second metal oxide blocking dielectric layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the first metal oxide blocking dielectric layers and each of the electrically conductive layers.

Three-dimensional memory device containing plural metal oxide blocking dielectric layers and method of making thereof

A semiconductor structure includes a doped single crystalline semiconductor material layer, a metal or metal alloy source contact layer located over a back side of the doped single crystalline semiconductor material layer, a dielectric isolation layer located over a front side of the doped single crystalline semiconductor material layer, an alternating stack of insulating layers and electrically conductive layers located over the dielectric isolation layer, a memory opening vertically extending through the alternating stack and the dielectric isolation layer and at least partially through the doped single crystalline semiconductor material layer, a memory film and a vertical semiconductor channel located within the memory opening, such that the vertical semiconductor channel vertically extends through the dielectric isolation layer and into the doped single crystalline semiconductor material layer, and a single crystalline semiconductor pedestal contacting the doped single crystalline semiconductor material layer and the vertical semiconductor channel.

Three-dimensional memory device containing epitaxial pedestals and top source contact

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.

Three dimensional memory device and method of making thereof by forming channel and memory film after word line replacement

A memory die includes source-select-level electrically conductive strips laterally spaced apart by source-select-level dielectric isolation structures, an alternating stack of word-line-level electrically conductive layers and insulating layers; and source strips located on an opposite side of the source-select-level electrically conductive strips. Each of the source strips has an areal overlap with only a respective one of the source-select-level electrically conductive strips. Memory stack structures vertically extend through the alternating stack and a respective subset of the source-select-level electrically conductive strips. A logic die may be bonded to the memory die on an opposite side of the source strips. Each source strip is electrically connected to a respective group of memory stack structures laterally surrounded by a respective source-select-level electrically conductive strip.

Three-dimensional memory device with isolated source strips and method of making the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, a vertical stack of discrete silicon nitride memory elements located at levels of the electrically conductive layers, and a vertical stack of discrete silicon oxide blocking dielectric structures laterally surrounding the vertical stack of discrete silicon nitride memory elements. Each of the silicon oxide blocking dielectric structures includes a silicon oxynitride surface region, and an atomic concentration of nitrogen atoms within the silicon oxynitride surface region decreases with a lateral distance from an interface between the silicon oxynitride surface region and a respective one of the silicon nitride memory elements.

Three-dimensional memory device with discrete charge storage elements and methods for forming the same

A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Memory openings, contact via cavities, or backside trenches may be used as access points for removing the sacrificial material layers.

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.

Three-dimensional memory device containing amorphous and crystalline blocking dielectric layers

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over at least one source layer, and groups of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source-side select gate electrodes can be laterally spaced apart by source-select-level dielectric isolation structures. Alternatively or additionally, the at least one source layer may include a plurality of source layers. A group of memory opening fill structures can be selected by selecting a source layer and/or by selecting a source-level electrically conductive layer.

Three-dimensional memory device with separated source-side lines and method of making the same

A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.

Memory die with source side of three-dimensional memory array bonded to logic die and methods of making the same

A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions andconvexconcavesidewall portions.

On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same

Growing community of inventors

Yokkaichi, Japan

Masanori Tsutsumi