Kabushiki Kaisha Toshiba

Canon Kabushiki Kaisha

Micron Technology Incorporated

Isuzu Motors Limited

Masanobu Saito

Hiroshi Iwai

Mizuki Ono

Hisayo S Momose

Takashi Yoshitomi

Shuji Tanaka

Yoshiaki Fukuzumi

Jun Fujiki

Tatsuya Ohguro

Yoshihiko Kamata

Masashi Yoshida

Shinichi Nakamura

Shunji Nakamura

Yukihiro Ushiku

Satoshi Matsuda

Yasushi Akasaka

Junji Araya

Yasuhiro Katsumata

Hideaki Nii

Toru Tanzawa

Yoshio Ozawa

Yuji Takeuchi

Yasushi Shimizu

Hitoshi Shiga

Toshio Miyamoto

Shigehiko Saida

Hiroki Kisu

Yohji Tomoyuki

Gaku Konishi

Shinji Sato

Hiroshi Satoh

Seiji Yamaguchi

Yasunari Watanabe

Takayuki Namiki

Satoru Inami

Keiji Okano

Seiichi Shinohara

Satoru Motohashi

Kazunori Hashimoto

Akira Domon

Claudio Fiegna

Tatsuya Ooguro

Hiroyuki Adachi

Atsushi Toda

Noribumi Koitabashi

Hiroshi Sato

Kazushi Watanabe

Yoshihiro Ito

Tadayuki Tsuda

Isao Ikemoto

Yasushi Sato

Shinya Noda

Jun Ito

Kimio Nakahata

Masaharu Ohkubo

Yasumasa Ohtsuka

Yoshikazu Sasago

Kazumi Sekine

Yukihiro Ohzeki

Koichi Okuda

Kazunori Kobayashi

Kazuhiro Okubo

Akira Hayakawa

Katsuhiko Nishimura

Tomomi Kakeshita

Tatsunori Ishiyama

Minoru Matsuguma

Yoji Tomoyuki

Kazuhisa Maruyama

Marehiko Hirajima

Jun Haruna

Fumitaka Matsumoto

Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells, a data line, a plurality of sets of field-effect transistors with each of the sets of field-effect transistors between the data line and a respective string of series-connected memory cells and having N field-effect transistors that are fabricated to have a respective binary permutation of two threshold voltages of a plurality of possible binary permutations of two threshold voltages having N positions, and N select lines that are each connected to a control gate of a respective field-effect transistor of each of the sets of field-effect transistors.

Apparatus containing memory array structures having multiple sub-blocks

Methods of forming integrated circuit structures for a capacitive sense NAND memory include forming a first semiconductor overlying a dielectric, forming a second semiconductor to be in contact with a first end of the first semiconductor, forming a third semiconductor to be in contact with a second end of the first semiconductor opposite the first end of the first semiconductor, forming a vertical channel material structure overlying the first semiconductor and having a channel material capacitively coupled to the first semiconductor, and forming a plurality of series-connected field-effect transistors adjacent the vertical channel material structure.

Methods of forming integrated circuit structures for capacitive sense NAND memory

Arrays of memory cells might include a first upper data line, a second upper data line, a lower data line, a first pass gate selectively connected to the lower data line, a second pass gate connected to the first pass gate and selectively connected to the lower data line, a third pass gate selectively connected to the lower data line, a fourth pass gate connected to the third pass gate and selectively connected to the lower data line, unit column structures selectively connected to a respective one of the upper data lines and capacitively coupled to a first channel of a respective one of the pass gates, and control lines capacitively coupled to a second channel of a respective one of the pass gates.

Memory array structures for capacitive sense NAND memory

Arrays of memory cells might include a data line, a source, a plurality of pass gates connected in series between the data line and the source, a plurality of unit column structures each having a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of its respective plurality of series-connected non-volatile memory cells and a channel of each field-effect transistor of its respective plurality of series-connected field-effect transistors are selectively connected to one another, and a plurality of backside gate lines each connected to the second control gate of a respective pass gate of the plurality of pass gates, wherein, for each unit column structure of the plurality of unit column structures, the channel of a particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates.

Sense line structures in capacitive sense NAND memory

Memory might include a plurality of series-connected non-volatile memory cells, a plurality of series-connected first field-effect transistors connected in series with the plurality of series-connected non-volatile memory cells, and a second field-effect transistor, wherein the channel of the second field-effect transistor is capacitively coupled to channels of the plurality of series-connected first field-effect transistors. The memory might further include a controller configured to cause the memory to selectively activate a selected non-volatile memory cell, activate each remaining non-volatile memory cell, increase a voltage level of the respective channel of each first field-effect transistor, selectively discharge the voltage level of the respective channel of each first field-effect transistor through the selected non-volatile memory cell, and determine whether the second field-effect transistor is activated in response to a remaining voltage level of the respective channel of each first field-effect transistor.

Access operations in capacitive sense NAND memory

An array of memory cells might include a first data line, a second data line, a source, a capacitance selectively connected to the first data line, a string of series-connected non-volatile memory cells between the first data line and the capacitance, and a pass gate selectively connected between the second data line and the source, wherein an electrode of the capacitance is capacitively coupled to a channel of the pass gate.

Capacitive sense NAND memory

Memory might include a non-volatile memory cell, a capacitance selectively connected to the non-volatile memory cell, a field-effect transistor having a channel capacitively coupled to an electrode of the capacitance, and a controller for access of the non-volatile memory cell configured to cause the memory to increase a voltage level of the electrode of the capacitance, selectively discharge the voltage level of the electrode of the capacitance through the non-volatile memory cell responsive to a data state stored in the non-volatile memory cell, and determine whether the field-effect transistor is activated in response to a remaining voltage level of the electrode of the capacitance.

Arrays of memory cells a plurality of sense lines each having a respective plurality of pass gates connected in series between a second data line and a source, and having a respective subset of unit column structures capacitively coupled to first channels of its respective plurality of pass gates, wherein, for each sense line of the plurality of sense lines, each unit column structure of its respective subset of unit column structures is connected to a respective first data line of a respective subset of first data lines.

Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.

Memory device including multiple gate-induced drain leakage current generator circuits

Embodiments of the present invention include an image bearing member arranged to bear an electrostatic latent image, a charging member contacting the image bearing member to charge a surface of the image bearing member with application of a DC voltage to the charging member, a current detection unit arranged to detect a DC current flowing in the charging member, and a control unit configured to control the voltage applied to the charging member, wherein a plurality of different DC voltages are successively applied to the charging member during a period of no image formation until a change amount of change in the DC current with respect to change in the DC voltage becomes not larger than a predetermined value, and the control unit controls a DC voltage applied to the charging member during a period of image formation based on a result detected by the current detection unit.

Image forming apparatus

A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

Non-volatile memory cell

Semiconductor device and method of manufacturing the same

In an image processing apparatus that includes an order placement means for executing an operation associated with order placement of an expendable used in an image forming apparatus, data associated with image formation is accumulated to have a timing associated with order placement as a trigger, and the operation of the order placement means is controlled on the basis of the accumulated value. In this manner, redundant orders for expendables can be prevented.

Image processing apparatus, method of placing order for expendables of image processing apparatus, storage medium, and program

A semiconductor device comprises: a p-type semiconductor substrate (); an insulating film (); a gate electrode () formed an the substrate via the insulating film; and an n-type source/drain region () formed on both sides of a channel forming region () located under the gate electrode () formed on the substrate (). In particular, the thickness (T) of the insulating film () is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (L) of the gate electrode () is determined to be equal to or less than 0.3 &#x3bc;m; and further a voltage applied to the gate electrode () and the drain region () is determined a be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.

MOSFET with a thin gate insulating film

Growing community of inventors

Chiba, Japan

Masanobu Saito