Hitachi, Ltd.

Sumco Corporation

Kyushu University

Renesas Electronics Corporation

Renesas Technology Corp.

Agency of Industrial Science and Technology

Semiconductor Technology Academic Research Center

Masanobu Miyao

Masao Tamura

Tokuo Kure

Makoto Ohkura

Hideo Sunami

Kiyokazu Nakagawa

Nobuyuki Sugii

Shinya Yamaguchi

Yoshifumi Kawamoto

Terunori Warabisako

Takashi Tokuyama

Eiichi Murakami

Nobuyoshi Natsuaki

Iwao Takemoto

Katsuhiro Shimohigashi

Yoshio Sakai

Masahiro Moniwa

Toshiaki Masuhara

Osamu Minato

Yasuo Wada

Shinji Shimizu

Mitsumasa Koyanagi

Koji Matsumoto

Takashi Ohshima

Kikuo Kusukawa

ShinIchiro Kimura

Kiyonori Ohyu

Masahiko Nakamae

Masaharu Ninomiya

Naotsugu Yoshihiro

Seang-kee Park

Taizoh Sadoh

Masao Kondo

Masakazu Aoki

Ichiro Mizushima

Shoji Shukuri

Yoshinobu Kimura

Shinichiro Kimura

Isao Yoshida

Tohru Nakamura

Yoichi Tamaki

Ryo Haruta

Toshifumi Ozaki

Haruhisa Ando

Kiichiro Mukai

Kazuhiko Sagara

Masaaki Nakai

Masaki Yoshimaru

Hiroshi Ishihara

Akitoshi Ishizaka

Tadashi Suzuki

Yuuichi Madokoro

Yasushiro Nishioka

Hiroshi Nakashima

Takuya Maruizumi

Hiroo Usui

Hiroyuki Eto

Shiya Ohba

At least first and second SiGe(0&#x2266;x&#x2266;1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second SiGe(0&#x2266;x&#x2266;1) layers. A lattice constant of the first SiGe(0&#x2266;x&#x2266;1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second SiGe(0&#x2266;x&#x2266;1) layer is matched with a lattice constant of the second material layer.

Semiconductor device including a plurality of different functional elements and method of manufacturing the same

In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layerto a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.

Semiconductor device and semiconductor substrate having selectively etched portions filled with silicon germanium

A strained Si&#x2014;SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layeron an SOI substratehaving an Si layerand a buried oxide film; forming protective filmson the surface of the SiGe mixed crystal layer; implanting light element ions into a vicinity of the interface between the Si layerand the buried oxide film; performing a first heat treatment at a temperature in the range of 400 to 1000&#xb0; C.; performing a second heat treatment at a temperature not lower than 1050&#xb0; C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050&#xb0; C. under an inert atmosphere; removing the Si oxide filmformed on the surface; and forming a strained Si layer

Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the same

A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided. The method includes the steps of: (a) forming an SiGe mixed crystal layerand a first Si layerin this order on the surface of a silicon wafer; (b) forming an SiOlayeron top of the first Si layer and/or a support wafer; (c) forming a layered productby stacking the silicon wafer and the support wafer with the SiOlayer being placed therebetween; (d) forming a second Si layerby thinning the silicon wafer of the layered product; (e) implanting hydrogen ion and/or rare gas ion, such that ionic concentration peaks in a predetermined area; (f) subjecting the layered product to a first heat treatment; and (g) carrying out a second heat treatment following the first heat treatment, thereby relaxing the SiGe mixed crystal layer and diffusing Ge through portions of the first Si layer and the second Si layer.

Method for manufacturing semiconductor wafer including a strained silicon layer

In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.

Semiconductor device and semiconductor substrate

To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.

Semiconductor device, method of making the same and liquid crystal display device

To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.

An electronic apparatus employs a polycrystalline semiconductor thin film structure formed of an insulating substrate and a plurality of polycrystalline layers laminated on the insulating substrate. A plurality of transistors are formed at the surface of the polycrystalline semiconductor thin film structure, each transistor being formed in a region of one of a plurality of crystal grains disseminated on the surface of the polycrystalline layers. A number of crystal grains in each of the polycrystalline layers is gradually reduced from a lower layer to an upper layer.

Electronic apparatus having polycrystalline semiconductor thin film structure

The present invention provides an apparatus having a semiconductor device including a plurality of transistors formed on respective single crystal silicon regions of enlarged grain size. On a polycrystalline silicon layer, projections at regular intervals are formed by using anisotropic etching and a photomask. The tips of projections are composed of single crystal silicon of a specific crystal orientation selectively left by the anisotropic etching, which is a candidate for nuclei of amorphous silicon to be deposited thereon. By iterating the above process a plurality of times, and by gradually enlarging the pitch, span, size and height of projections, the size of the crystal grains of silicon at the surface may be enlarged to the extent required. Thereby, silicon crystal grains of large grain size with the crystal orientation aligned may be formed at controllable positions.

ELECTRONIC APPARATUS HAVING SEMICONDUCTOR DEVICE INCLUDING PLURALITY OF TRANSISTORS FORMED ON A POLYCRYSTALLINE LAYERED STRUCTURE IN WHICH THE NUMBER OF CRYSTAL GRAINS IN EACH POLYCRYSTALLINE LAYER IS GRADUALLY REDUCED FROM LOWER TO UPPER LAYER

Configurations of a light signal communication apparatus and an optical communication system suitable for speeding-up of the transmission of information based on a light signal and an increase in the capacity for the information transmission are disclosed. On the light signal transmitting side, excitation light is supplied to an active medium in accordance with a transmission signal to cause induced emission within the active medium, thereby generating signal light. The excitation light causes spontaneously-emitted light to fall on a semiconductor layer, and a voltage pulse corresponding to transmission information is applied to modulate the refractive index of the semiconductor layer, thereby Bragg-reflecting a specific wavelength component, after which it is sent to the active medium as the excitation light. The Bragg reflection and induced emission incident to it exhibit excellent response to a voltage signal having a pulse width of 1&times;10 seconds or less. It is therefore possible to implement an optical communication system having a transmission rate up to 100 Gb/s with one light signal.

Optical communication equipment and system

A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.

Semiconductor memory with trench capacitor

A transistor having a high carrier mobility and suited for a high-speed operation can be formed by utilizing a fact that the carrier mobility in a strained germanium layer is large. A strain control layer is provided beneath the germanium layer to impose a compressive strain on the germanium layer, and the composition of the strain control layer in a predetermined range is used to generate the compressive strain surely.

Transistor provided with strained germanium layer

A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Semiconductor memory

A method of producing a hetero structure, including the steps of depositing hydrogen atoms or halogen atoms onto a surface of a first single crystal layer formed of semiconductor or metal silicide, and forming a second single crystal layer on the first single crystal layer by hetero epitaxial growth, the second single crystal layer being formed of semiconductor or metal silicide different from the material of the first single crystal layer, wherein both of the steps are continuously conducted without taking the hetero structure out of a producing device. Further, the number of the hydrogen atoms or the halogen atoms to be deposited is equal to or in the range of .+-.50% with reference to the number of dangling bonds existing in a hetero interface between the first single crystal layer and the second single crystal layer, so that the lattice defects in the hetero interface can be reduced.

Method of producing hetero structure

Growing community of inventors

Fukuoka, Japan

Masanobu Miyao