Sony Corporation

Sony Semiconductor Solutions Corporation

Sony Electronics Inc

Masanaga Fukasawa

Takeshi Nogami

Nobutoshi Fujii

Shingo Kadomura

Kenichi Aoyagi

Yoshiya Hagimoto

Yoshihisa Kagawa

Ikue Mitsuhashi

Tetsuya Tatsumi

Tokihisa Kaneguchi

Akiko Hirata

Toshiaki Hasegawa

Koichi Ikeda

Nobuyuki Kuboi

Hideyuki Kito

Kazuhiro Karahashi

Satoshi Hamaguchi

A first etching method of an oxide semiconductor film according to an embodiment of the present disclosure includes: forming a reduction layer in an oxide semiconductor film with use of a reducing gas; and sputtering the reduction layer with use of a rare gas.

Etching method of oxide semiconductor film, oxide semiconductor workpiece, and electronic device

In an etching method for an oxide semiconductor film according to an embodiment of the present disclosure, a modified layer is formed in the oxide semiconductor film by using a first rare gas and the modified layer is sputtered by using a second rare gas different from the first rare gas.

Etching method for oxide semiconductor film

Provided is a solid-state imaging device capable of reducing bonding defects when two substrates are bonded to each other, and a method for manufacturing the solid-state imaging device. The solid-state imaging device includes a first substrate including a first electrode formed with a metal, and a second substrate that is a substrate bonded to the first substrate, the second substrate including a second electrode formed with a metal, the second electrode being bonded to the first electrode. In at least one of the first substrate or the second substrate, a diffusion preventing layer of the metal is formed for a layer formed with the metal filling a hole portion, the metal forming the electrodes.

Solid-state imaging device and method for manufacturing the same

An etching method includes inputting, to a setting unit, at least electric power, a pressure, and a gas flow rate, performing etching processing in a chamber, on the basis of a value inputted to the setting unit, and calculating an ion energy distribution mathematical function, by using a measured value upon the etching processing.

Etching method and etching processing apparatus

The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.

Semiconductor device and solid-state imaging device

Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.

Semiconductor device and manufacturing method of the same

The simulation method is for predicting a damage amount due to ultraviolet rays in manufacturing a semiconductor device. The method includes: calculating particle density by performing simulation based on a differential equation for the particle density; calculating emission intensity at each wavelength in a visible wavelength region based on the calculated particle density; obtaining an electron energy distribution function by comparing the calculated emission intensity at each wavelength in the visible wavelength region with an actually detected emission spectrum in the visible wavelength region with reference to information on emission species and an emission wavelength in a target manufacturing process; predicting an emission spectrum in an ultraviolet wavelength region by using the electron energy distribution function and a reaction cross-sectional area relating to the emission species; and predicting a damage amount due to the ultraviolet rays based on the predicted emission spectrum in the ultraviolet wavelength region.

Predicting ultraviolet ray damage with visible wavelength spectroscopy during a semiconductor manufacturing process

An arrangement of semiconductor chips is provided. The arrangement includes a plurality of stacked semiconductor chips each including an integrated circuit. At least one via is formed through the thickness of at least one of the semiconductor chips. A carbon nanotube conductor is formed in the via. The conductor has first and second opposite ends. The first end of the conductor is selectively interconnected with the integrated circuit of its semiconductor chip and the second end of the conductor is selectively interconnected with the integrated circuit of another of the semiconductor chips.

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Tokyo, Japan

Masanaga Fukasawa