Upi Semiconductor Corporation

Masamichi Yanagida

Nobuyoshi Matsuura

Masashi Koyano

Hiroki Arai

The present invention provides a semiconductor device that can achieve miniaturization or thinning of the size of the package while maintaining the characteristic of the MOSFET and reducing the on-resistance value, and a portable apparatus using the same. The gate electrodesandof the semiconductor chipare disposed in the vicinity of the two side surfaces of the longitudinal direction (the x axis direction on the page) of the package, and the gate terminalandthat is mounted with the gate electrodesandin a flip-chip manner are extended in the longitudinal direction of the packageand are derived to the outside from the two side surfacesA andB. Based on the configuration, it is capable of maximizing the size of the semiconductor chip with respect to the size of the package, and it is able to realize the high performance of the element characteristic for the module.

Semiconductor device and portable apparatus using the same

A semiconductor device manufacturing method is disclosed. The semiconductor device manufacturing method includes: a preparation step of preparing a semiconductor wafer; a removal step of removing a thickness part of the semiconductor wafer; and a cutting step of cutting the semiconductor wafer. In the removal step, a rib-shaped portion partially raised on a second main surface of the semiconductor wafer is used as an alignment mark, so that a cutter can align with the semiconductor wafer.

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Gunma-ken, Japan

Masamichi Yanagida