Nec Corporation

Masamichi Kawarabayashi

Koichi Sato

Naotaka Maeda

Hideyuki Emura

Takuo Nakaki

A method designs a logic circuit having a flip-flop which performs an on and off operation in response to a timing clock and a feedback loop. With such a structure, a logic circuit portion which operates in accordance with an enable signal automatically is extracted. Further, the logic circuit portion is formed by the use of a gated clock obtained by gating the timing clock via the enable signal. Thereby, the number of on and off operations of the flip-flop in response to the timing clock can be largely reduced.

Method of changing logic circuit portion into gated clock portion and recording medium storing a program for carrying out the method

A delay optimization system including a layout processing unit for receiving the input of circuit specification of a target circuit to conduct layout, as well as extracting wiring information, an optimization processing unit for conducting optimization with reference to the wiring information, as well as generating circuit change information and inserted buffer information, and a constraints violations determining unit for determining whether a circuit generated as a result of the layout by the layout processing unit satisfies delay constraints set for the target circuit, the layout processing unit executing initial layout based only on circuit information synthesized based on the circuit specification of the target circuit and re-layout with reference to the circuit change information and inserted buffer information generated by the optimization processing unit.

Delay optimization system to conduct optimization for satisfying delay

An optimization apparatus comprises a hierarchical circuit specification input for entering a logic circuit having a hierarchical structure, a delay constraint input for entering delay constraints of the logic circuit, a circuit database for storing and holding the logic circuit and delay constraint, a timing analyzer for performing the timing analysis of the logic circuit, a delay constraint distributor for distributing the delay constraints to each hierarchical configuring the logic circuit according to optimization possibility of the logic circuit, an optimizing unit for performing the delay optimization of the logic circuit according to the delay constraints distributed to the respective hierarchical sub-circuit of the logic circuit, a library input for entering library information to be used for the timing analysis of the logic circuit, a library database for holding the library information, and an output for outputting the optimized logic circuit.

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Tokyo, Japan

Masamichi Kawarabayashi