Semiconductor Technology Academic Research Center

Tohoku University

Masaki Yoshimaru

Junichi Koike

Noriyoshi Shimizu

Mayumi Nakasato

Takashi Ono

Sumio Hosaka

Hayato Sone

Hideki Shibata

Takamasa Usui

Makoto Wada

Hayato Nasu

Shingo Takahashi

Satoshi Nishikawa

Koji Arita

Yoshito Fujii

Jun Iijima

Kazuyoshi Maekawa

Ryotaro Yagi

Hisashi Yano

Hitoshi Tanaka

Ichiro Mizushima

Noriaki Matsunaga

Masanobu Miyao

Seiji Samukawa

Haruhiko Takahashi

Koji Usuda

Masaharu Oshima

Hiroshi Nakashima

Eiichi Kondoh

Ziyuan Liu

Taizoh Sadoh

Kunitoshi Tajima

Michiru Hirose

Masayuki Satoh

Liu Guo-lin

Kazuto Ikeda

Shigeo Yasuhara

Shingo Kadomura

Tsutomu Shimayama

At least first and second SiGe(0&#x2266;x&#x2266;1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second SiGe(0&#x2266;x&#x2266;1) layers. A lattice constant of the first SiGe(0&#x2266;x&#x2266;1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second SiGe(0&#x2266;x&#x2266;1) layer is matched with a lattice constant of the second material layer.

Semiconductor device including a plurality of different functional elements and method of manufacturing the same

Disclosed is a low dielectric constant insulating film formed of a polymer containing Si atoms, O atoms, C atoms, and H atoms, which includes straight chain molecules in which a plurality of basic molecules with an SiO structure are linked in a straight chain, binder molecules with an SiO structure linking a plurality of the straight chain molecules. The area ratio of a signal indicating a linear type SiO structure is 49% or more, and the signal amount of the signal indicating Si(CH) is 66% or more.

Low dielectric constant insulating film and method for forming the same

A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.

Semiconductor device having a multilevel interconnect structure and method for fabricating the same

A multilevel interconnect structure in a semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.

A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.

Semiconductor device with a barrier film

A phase-change channel transistor includes a first electrode; a second electrode; a memory layer provided between the first and second electrodes; and a third electrode provided for the memory layer with an insulating film interposed therebetween, wherein the memory layer includes at least a first layer formed from a phase-change material which is stable in either an amorphous phase or a crystalline phase at room temperature and a second layer formed from a resistive material, and wherein the resistance value of the second layer is smaller than the resistance value of the first layer in the amorphous phase, but is larger than the resistance value of the first layer in the crystalline phase.

Phase-change memory device, phase-change channel transistor and memory cell array

A multi-value recording phase-change memory device that can stably record multi-value information, and that can reproduce information with high reliability, comprises a first electrode layer, a second electrode layer, and a memory layerprovided between the first and second electrode layersandand containing a phase-change material layer formed from a phase-change material which is stable in either an amorphous phase or a crystalline phase at room temperature, wherein the memory layerincludes a plurality of mutually isolated sub-memory layers, andbetween the first and second electrode layersand

Multi-value recording phase-change memory device, multi-value recording phase-change channel transistor, and memory cell array

To reduce the voltage required to cause a phase transition from an amorphous phase to a crystalline phase, a phase-change memory device () comprises: a first electrode (); a second electrode (); and a memory layer () provided between the first () and second () electrodes, wherein the memory layer () includes at least a first layer () formed from a phase-change material which is stable in either the amorphous phase or the crystalline phase at room temperature, and a second layer () formed from a resistive material, and wherein the resistance value of the second layer () is smaller than the resistance value of the first layer () in the amorphous phase, but is larger than the resistance value of the first layer () in the crystalline phase.

Phase-change memory device, phase-change channel transistor, and memory cell array

A method for selectively forming an electric conductor, the method including disposing a processing target and a metal compound in an atmosphere including a supercritical fluid, the processing target having formed thereon at least one recess for providing an electric conductor, the metal compound including a metal serving as a main component of the electric conductor, and dissolving at least part of the metal compound in the supercritical fluid, selectively introducing the metal compound dissolved in the supercritical fluid into the recess in contact with a surface of the processing target, and coagulating in the recess the metal compound introduced into the recess to precipitate the metal from the metal compound, and coagulating the metal precipitated in the recess, thereby providing the electric conductor in the recess.

Method for selectively forming electric conductor and method for manufacturing semiconductor device

A stacked film has an insulating film containing hafnium formed above a silicon layer and a polysilicon layer formed on the insulating film. The stacked film is heated in an atmosphere containing oxygen and nitrogen and having the total pressure approximately equal to a partial pressure of the nitrogen.

Method of manufacturing an insulating film containing hafnium

A multi-value recording phase-change memory device that can stably record multi-value information, and that can reproduce information with high reliability, comprises a first electrode layera second electrode layerand a memory layerprovided between the first and second electrode layersandand containing a phase-change material layer formed from a phase-change material which is stable in either an amorphous phase or a crystalline phase at room temperature, wherein the memory layerincludes a plurality of mutually isolated sub-memory layersandbetween the first and second electrode layersand

A semiconductor device includes an interlevel insulating film disposed on a semiconductor substrate and having an opening formed therein. An interconnection main layer, which contains Cu as a main component, is embedded in the opening. A barrier film is interposed between the interlevel insulating film and the interconnection main layer within the opening. The barrier film contains, as a main component, a compound of a predetermined metal element with a component element of the interlevel insulating film.

Semiconductor device with a barrier film which contains manganese

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Masaki Yoshimaru