Hitachi High-Tech Corporation

Masaki Sugie

Kei Sakai

The present invention enables an overlay error between processors to be measured from a pattern image, the SN ratio of which is low. To this end, the present invention forms a secondary electron imagefrom a detection signal of a secondary electron detector, forms a reflected electron imagefrom a detection signal of a reflected electron detector, creates a SUMLINE profilethat is obtained by adding luminance information in the reflected electron image along the longitudinal direction of a line pattern, and calculates an overlay error of a sample by using position information about an upper layer pattern detected from the secondary electron image and position information about a lower layer pattern that is detected by using an estimation line patternestimated on the basis of the SUMLINE profile from the reflected electron image.

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Tokyo, Japan

Masaki Sugie