Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Masaki Inoue

Daigo Yamashina

Akira Ohdaira

Mitsuo Tanaka

Shinya Natsume

A semiconductor device includes: an active layer that is located in an SOI substrate, and in which an element included in a circuit is formed; a buried insulation layer that is located in the SOI substrate, and is in contact with the active layer; a deep trench isolation (DTI) region that is formed in the active layer to surround a whole formation region of the element in plan view, and extends from an upper surface to a lower surface of the active layer; and a first conductive film formed above the element. The DTI region has a first hole inside, and a film thickness of the first conductive film is greater than a thickness of the active layer.

Semiconductor device

A semiconductor device includes a drift diffusion region of a first conductivity type, a body diffusion region of a second conductivity type, a source diffusion region of the first conductivity type, an insulating film buried in a trench formed in an upper portion of the drift diffusion region and spaced apart from the body diffusion region, a drain diffusion region of the first conductivity type formed in an upper portion of the drift diffusion region and adjacent to the insulating film on the opposite side of the insulating film from the source diffusion region, and a gate electrode formed on a portion of the body diffusion region, the drift diffusion region, and a portion of the insulating film. The drift diffusion region includes a substrate inner region, and a surface region containing an impurity of the first conductivity type at a higher concentration than that of the substrate inner region.

Semiconductor device and method for fabricating the same

This invention aims at providing an inexpensive semiconductor device having a parasitic diode and lowering an hfe of a parasitic PNP transistor and a manufacturing method thereof. Such semiconductor device includes a P-type silicon substrate and a gate electrode formed above the P-type silicon substrate. The P-type silicon substrate includes an N-type well layer, an N-type buried layer, a P-type body layer, an N-type source layer formed in the P-type body layer, and a drain contact layer formed in the N-type well layer. The P-type body layer and the N-type source layer are formed by self alignment that uses the gate electrode as a mask. The N-type drain contact layer is formed opposite the N-type source layer across the P-type body layer formed below the gate electrode. The N-type buried layer is formed below the P-type body layer.

Growing community of inventors

Osaka, Japan

Masaki Inoue