Elpida Memory, Inc.

Hitachi, Ltd.

Other

Ps4 Luxco S.a.r.l.

Masakazu Ishino

Hiroaki Ikeda

Kunihiko Nishi

Yasuhiro Naka

Hiroyuki Tenmei

Kayoko Shibata

Nae Hisano

Ryohei Satoh

Yasunori Narizuka

Shiro Uchiyama

Hideharu Miyake

Tsuyoshi Tamaru

Shigeru Kobayashi

Mamoru Mita

Osamu Kasahara

Susumu Tsuzuku

Eisuke Nishitani

Shigeo Ohashi

Hiroki Nezu

Yasuo Osone

Osamu Yamada

Takashi Inoue

Naoya Kanda

Eiji Matsuzaki

Akira Yabushita

Hideo Sotokawa

Michifumi Kawai

Akihiro Kenmotsu

Akitoshi Hiraki

Eiji Matsuda

Masayuki Kyoui

Juichi Kishida

Syoozi Ikeda

Yoshitaka Chiba

Akihiro Kemmotsu

A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.

Semiconductor device having a liquid cooling module

A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

Semiconductor memory device and manufacturing method thereof

A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusionwhich is provided in low melting point metalfor electrically connecting mutually joined wafersand, and which defines an interval between mutually joined wafersandwithout being deformed at the time when low melting point metalis melted. A joining structure of wafersandis manufactured by using wafersand, at least one of which has protrusion. In the manufactured joining structure of wafersand, wafersandare electrically connected to each other by low melting point metal, and protrusion, which defines the interval between wafersandwithout being deformed at the time when low melting point metalis melted, is provided in low melting point metal

Wafer of circuit board and joining structure of wafer or circuit board

A semiconductor package includes a uniform thin insulating film covering the internal circuit formed on a silicon substrate. A plurality of thick island insulating films are formed underlying respective pad electrodes, which connect the internal circuit to an external circuit. The silicon substrate is polished from the bottom to have a thickness less than 0.6 mm. The thick island insulating films reduces an electrostatic capacitance of the pad electrodes to reduce the propagation delay of a signal passing through the pad electrodes.

Semiconductor device having a smaller electrostatic capacitance electrode

A method for manufacturing a semiconductor device includes the steps of forming first and second semiconductor wafers each including an array of chips and elongate electrodes, forming a groove on scribe lines separating the chips from one another; coating a surface of one of the semiconductor wafers with adhesive; bonding together the semiconductor wafers while allowing the groove to receive therein excessive adhesive; and heating the wafers to connect the elongate electrodes of both the semiconductor wafers.

Method for manufacturing a three-dimensional semiconductor device and a wafer used therein

A memory module of the present invention has a memory core chip for storing information, an interface chip for controlling data input/output, an interposer chip for transmitting/receiving data to/from the outside, and an external connection terminal provided in closest proximity to the interposer chip. A heat dissipating plate is provided in closest proximity to the interface chip. The interposer chip has a substrate made of a semiconductor material that is similar to the memory core chip, a land for holding the external connection terminal, a wire connected to the external connection terminal, and an insulating film for insulating the wire. The land, wire, and insulating film are integrally formed on one surface of the interposer chip.

Memory module with improved mechanical strength of chips

A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.

Bonding method of semiconductor and laminated structure fabricated thereby

A memory module of the present invention is provided with a memory core chip that is placed between an interface chip and an interposer chip and has a relay wire for electrically connecting these chips, an interposer chip that transmits type-information, that is information showing the type of the memory core chip, to the interface chip through the relay wire, and the interface chip that controls the memory core chip in accordance with the type-information received from the interposer chip.

Memory module that is capable of controlling input/output in accordance with type of memory chip

An electrode structure as well as the fabrication method thereof is disclosed which may enable successful pad layout conversion of interconnection electrode pads on the periphery of an associated IC chip to a grid array of rows and columns of terminal solder pads arranged occupying the entire area of the opposite surface of the chip while permitting use of a minimized length of wire leads for interconnection therebetween. This is achieved by (i) preparing a flat square IC chip which has an array of regularly spaced peripheral bonding pads the number of which along each of four chip sides is equally defined by a function of 2i(2i-1) where 'i' is an integer and which also has external connection pads made of aluminum, (ii) sequentially forming nickel and gold coat films on the chip by electroless plating techniques, (iii) electrically coupling by metal contacts using thermal compression-bonding techniques the peripheral bonding pads to the pad layout conversion substrate for rearrangement of the peripheral bonding pads into the grid array of solder pads, and (iv) filling an adhesion resin between the conversion substrate and the IC chip.

Electrode structure of a wiring substrate of semiconductor device having

A multilayer substrate which is fabricated by laminating a plurality of substrates, each comprising an insulation film, a plurality of via holes which pass through the upper surface to the lower surface of the insulation film, a wiring which is provided on the upper surface of the insulation film and the upper surface of the via holes and electrically connected with the via holes, a bonding member which is provided on the lower surfaces of the via holes and electrically connected with the via holes, and a bonding layer which is provided on the upper surface of the insulation film where the wiring is formed and the method of fabrication thereof whereby large costs reduction and high density effect can be obtained.

Multilayer substrates methods for manufacturing multilayer substrates

Electrode structure of wiring substrate of semiconductor device having

Growing community of inventors

Tokyo, Japan

Masakazu Ishino