Lsi Logic Corporation

Semiconductor Components Industries, LLC

Masaichi Eda

Philippe Schoenborn

Rongxiang Hu

Yongbae Kim

Sang-Yun Lee

Hiroaki Takikawa

Keith K Chao

Kai Zhang

Peter McGrath

Shumay X Dou

Dilip Vijay

Sarah Neuman

Shiqun Gu

Prasad Venkatraman

Wilbur G Catabay

Dean E Probst

Peter Austin Burke

Wei-Jen Hsia

Hong Lin

Hongqiang Lu

Jeffery Allen Neuls

Jim Elmer

In one embodiment, a method of forming a semiconductor device forms gate trenches in a semiconductor substrate. A portion of the material between the trenches is narrowed and another material is formed on sidewalls of the narrowed portion that is substantially not etched by an etchant that etches the material of the portion of the material between the trenches. Source and gate contact openings are formed together.

Method of forming a semiconductor device

A method of forming via structures between a first electrically conductive layer and a second electrically conductive layer. The first electrically conductive layer is formed, and a dielectric layer is formed over the first electrically conductive layer. A first photoresist layer is formed over the dielectric layer, and patterned with a first via hole pattern. The first via hole pattern includes via holes that are all disposed within a first distance one from another, called dense via holes, and excludes via holes that are disposed at greater than the first distance one from another, called isolated via holes. The dense via holes are etched into the dielectric layer at first etch conditions until the dense via holes are properly formed, and the first photoresist layer is removed. A second photoresist layer is formed over the dielectric layer, and is patterned with a second via hole pattern. The second via hole pattern excludes dense via holes and includes isolated via holes. The isolated via holes are etched into the dielectric layer at second etch conditions until the isolated via holes are properly formed, and the second photoresist layer is removed. Electrically conductive vias are formed within both the dense via holes and the isolated via holes, and the second electrically conductive layer is formed over the dielectric layer. Electrical continuity exists between the first electrically conductive layer and the second electrically conductive layer through the electrically conductive vias.

Reduced dry etching lag

A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Method of preventing resist poisoning in dual damascene structures

A method of making a semiconductor device includes providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. An upper surface of the second element slopes downwardly toward the upper surface of the first element. A first layer of a second substantially non-electrically conductive material is disposed over the upper surface of the first element and the upper surface of the second element. The first layer has a thickness in the vertical direction that is greater in an area over the downward slope of the second element than in an area over the first element. An etching process is performed such that the layer is perforated above the upper surface of the first element and imperforated in the vertically thicker area above the downwardly sloping upper surface of the second element.

Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene process

The subject matter described herein involves an improved etch process for use in fabricating integrated circuits on semiconductor wafers. The selectivity of the etch process for silicon carbide versus silicon oxide, organo silica-glass or other low dielectric constant type material is enhanced by adding hydrogen (H2) or ammonia (NH3) or other hydrogen-containing gas to the etch chemistry.

High selectivity SiC etch in integrated circuit fabrication

The present invention is directed to a silicon carbide anti-reflective coating (ARC) and a silicon oxycarbide ARC. Another embodiment is directed to a silicon oxycarbide ARC that is treated with oxygen plasma. The invention includes method embodiments for forming silicon carbide layers and silicon oxycarbide layers as ARC's on a semiconductor substrate surface. Particularly, the methods include introducing methyl silane materials into a process chamber where they are ignited as plasma and deposited onto the substrate surface as silicon carbide. Another method includes introducing methyl silane precursor materials with an inert carrier gas into the process chamber with oxygen. These materials are ignited into a plasma, and silicon oxycarbide material is deposited onto the substrate. By regulating the oxygen flow rate, the optical properties of the silicon oxycarbide layer can be adjusted. In another embodiment, the silicon oxycarbide layer can be treated with oxygen plasma.

Anti-reflective coatings for use at 248 nm and 193 nm

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Gresham, OR, United States of America

Masaichi Eda