Kabushiki Kaisha Toyota Chuo Kenkyusho

Toyota Jidosha Kabushiki Kaisha

Denso Corporation

Toyoda Gosei Co., Ltd.

Masahito Kodama

Tsutomu Uesugi

Kazuyoshi Tomita

Takashi Suzuki

Masahiro Sugimoto

Seiji Nagai

Shinichi Hoshi

Sachiko Kawaji

Yoshinori Tsuchiya

Kenji Itoh

Eiko Hayashi

A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on the substrate that is configured by a compound semiconductor mainly having a group III nitride; a gate structure configured by a gate electrode on the channel forming layer with a gate insulating film interposed therebetween; and a source electrode and a drain electrode on the channel forming layer at both sides of the gate structure respectively, a collapse inhibiting layer on the channel forming layer in an element region of the channel forming layer where the switching device is arranged that is configured by an insulating material; and a leakage inhibiting layer on the channel forming layer in an element isolation region of the channel forming layer surrounding the element region that is configured by an insulating material different from that of the collapse inhibiting layer.

Semiconductor device and method of manufacturing the same

The invention provides a method for producing a group III nitride based semiconductor having a reduced number of crystal defects. A GaN layeris epitaxially grown on a sapphire substratehaving C-plane as a main plane (FIG.A). Then, the layer is wet-etched by use of a 25% aqueous TMAH solution at 85&#xb0; C. for one hour, to thereby form an etch pit(FIG.B). Then, a GaN layeris grown on the GaN layerthrough the ELO method (FIG.C). The thus-formed GaN layerhas a screw dislocation density lower than that of the GaN layer

Group III nitride based semiconductor and production method therefor

A GaN layergrows in vertical direction on a GaN layerwhere neither a first masknor a second maskis formed. When thickness of the GaN layerbecomes larger than that of the first mask, it began to grown in lateral direction so as to cover the first mask. Because the second maskis not formed on the upper portion of the first mask, the GaN layergrows in vertical direction. On the contrary, at the upper region of the GaN layerwhere the maskis not formed, the second maskis formed like eaves, the growth of the GaN layerstops and threading dislocations propagated with vertical growth also stops there. The GaN layergrows in vertical direction so as to penetrate the region where neither the first masknor the second maskis formed. When the height of the GaN layerbecomes larger than that of the second mask, the GaN layerbegins to grow in lateral direction again and covers the second mask. After the GaN layercompletely covers the second mask, it began to grow in vertical direction.

Production method of III nitride compound semiconductor, and III nitride compound semiconductor element based on it

There is provided a method of manufacturing a vertical semiconductor device including a structural section in which an n -type semiconductor region and a p -type semiconductor region are arranged alternately without filling trenches by epitaxial growth. A p -type silicon layer ( ) which becomes a p -type semiconductor region ( ) is formed. An n -type semiconductor region ( ) is formed by diffusing n-type impurities into the p -type silicon layer ( ) through the sidewalls of first trenches ( ) formed in the p -type silicon layer ( ).

Vertical semiconductor device having alternating conductivity semiconductor regions

Disclosed is a semiconductor device including a lateral MOS element which comprises a p-type silicon substrate; a first semiconductor layer of an n-type constituting a drift region; a second semiconductor layer of the p-type selectively provided in the first semiconductor layer, and constituting a body region, in which a channel region is partially formed; a third semiconductor layer of the n-type selectively provided in a surface of the second semiconductor layer, and constituting a source region; a fourth semiconductor layer of the n-type provided in the first semiconductor layer, and constituting a drain region; and a trench gate. The trench gate is constructed such that a trench formed in the first semiconductor layer is filled with a gate electrode with an insulating film interposed therebetween. The trench gate is formed such that at least a bottom thereof is in contact with the semiconductor substrate. The semiconductor device of the present invention prevents a high electric field at a corner of the bottom of the trench gate, thus achieving its high breakdown voltage.

Semiconductor device including lateral MOS element

A vertical semiconductor device having an insulated gate structure makes use of a double-gate structure. The double-gate structure dramatically reduces the channel resistance, JFET resistance, and epitaxial resistance of the on-resistance of the power MOSFET, and implements an adequate breakdown voltage due to the effect of gate bias. In principle, a first gate and second gate having mutually facing portions are driven synchronously. This causes first and second channels to be formed in correspondence with first and second gates, and the currents flowing through these first and second channels form the on-current for this power device having a vertical structure.

Growing community of inventors

Aichi, Japan

Masahito Kodama