Mitsubishi Denki Kabushiki Kaisha

Masahiro Yoneda

Hidekazu Oda

Shinichi Satoh

Koichi Moriizumi

Akira Tokui

Yoshio Kohno

Masahiro Hatanaka

Hiroshi Koyama

Hideaki Arima

Tadashi Nishimura

Yoshinori Okumura

Takaaki Fukumoto

Hiroji Ozaki

Yoshihiro Hirata

Wataru Wakamiya

Ikuo Ogoh

Masao Nagatomo

Shiro Hine

A fine pattern forming apparatus includes a stage and an opposed electrode at least one of which is made of a magnetic material. A magnetic field is applied to this stage or opposed electrode to provide a predetermined gap between the stage and the opposed electrode for a fine pattern formation. In consequence, optimum etching conditions (including etching uniformity, etch rate and etching direction) can be assured without generating dust. As a result, damage caused by the plasma can be reduced, and the etch rate can be increased.

Method of forming a fine pattern

A capacitor of a semiconductor memory device includes a planar type capacitor portion formed on a surface of an impurity region and a stacked type capacitor portion extending above the gate electrode. The stacked capacitor portion has a three-layer structure of polycrystalline silicon in which upper, lower and side surfaces of a lower electrode are surrounded by a dielectric layer and the upper electrode. A portion of a dielectric layer in the stacked capacitor portion is coupled to another dielectric layer formed on the surface of one impurity region. The capacitor has a planar type capacitor provided in the planar area of occupation of the stacked capacitor portion, whereby the capacitance of the capacitor can be increased without increasing the planar area of occupation.

Semiconductor memory device having a stacked type capacitor and

A fine pattern forming apparatus includes an elastic wave generating device which is provided on the wall of a vacuum chamber. A fine pattern forming method involves formation of a fine pattern while an elastic wave is being applied to the vacuum chamber by the elastic wave generating device. Since the fine pattern is formed while the elastic wave is applied to the vacuum chamber the, uniformity of the plasma density and of the electron density is improved and attachment of reaction products to the vacuum chamber is prevented.

Apparatus and method for forming a fine pattern

A method of forming a minute pattern with controlled resist profile by using chemically amplifying type resist and deep UV ray is disclosed. A positive chemically amplifying type resist is applied on a silicon substrate, to form a resist film of the resist on the silicon substrate. The resist film is selectively irradiated with KrF excimer laser beam by using a photomask. Thereafter, an electric field directed vertically downward is applied to the resist film while the resist film is heated. According to this method, H.sup.+ ions which are catalyst for destroying the dissolution inhibiting capability of the dissolution inhibitor generated in the resist film move vertically downward, so that diffusion of the H.sup.+ ions in the lateral direction during heating can be prevented. Consequently, a positive minute pattern having sidewall formed vertical to the substrate can be provided.

Method of forming minute patterns using positive chemically amplifying

Fine pattern forming apparatus

Method for manufacturing semiconductor memory device having a stacked

A MOS FET comprises a gate electrode and source and drain regions. Conductive layers for electrode are formed on surfaces of the source and drain regions. The conductive layers for electrode are formed by a multilayer structure including a high melting point metal silicide film in contact with the source and drain regions and a polycrystaline silicon layer formed thereon. The gate electrode is formed of polysilicon. The gate electrode has a structure in which part of the gate electrode extends over the conductive layers for electrode formed on the source and drain regions. Such structure reduces the resistance of the interconnection layers for electrodes and realizes reduction in width of the gate electrode. In the manufacturing method, the patterning of the conductive layers for electrodes on the surface of the source/drain regions comprises the steps of etching the polycrystalline silicon layer by dry etching, and ethcing the high melting point metal silicide layer by wet etching. The wet etching enables etching process without damaging the silicon substrate surface.

Multiple layer electrode structure for semiconductor device and method

A method of forming a minute pattern with controlled resist profile uses a chemically amplifying type resist and deep UV rays. Microposit SAL601-ER7 is applied on a silicon substrate, to form a resist film of the resist on the silicon substrate. The resist film is selectively irradiated with KrF excimer laser beam by using a photomask. Thereafter, an electric field directed vertically downward is applied to the resist film while the resist film is heated. According to this method, H.sup.+ ions which are a catalyst for cross linking generated in the resist film move vertically downward, so that diffusion of the H.sup.+ ions in the lateral direction during heating can be prevented. Consequently, negative minute patterns having sidewalls formed vertical to the substrate can be provided.

Method of forming minute patterns using chemically amplifying type resist

A MOS FET comprises a gate electrode and source and drain regions. Conductive layers for electrode are formed on surfaces of the source and drain regions. The conductive layers for electrode are formed by a multilayer structure including a high melting point metal silicide film in contact with the source and drain regions and a polycrystalline silicon layer formed thereon. The gate electrode is formed of polysilicon. The gate electrode has a structure in which part of the gate electrode extends over the conductive layers for electrode formed on the source and drain regions. Such structure reduces the resistance of the interconnection layers for electrodes and realizes reduction in width of the gate electrode. In the manufacturing method, the patterning of the conductive layers for electrodes on the surface of the source/drain regions comprises the steps of etching the polycrystalline silicon layer by dry etching, and etching the high melting point metal silicide layer by wet etching. The wet etching enables etching process without damaging the silicon substrate surface.

A dynamic type semiconductor device comprises a memory cell array including a plurality of cell groups, each of the cell groups including four adjacent memory cells disposed in a point symmetry fashion, with a single contact hole formed at the center of the point symmetry to be common to the four memory cells, in which the four memory cells and bit lines are connected through the single contact hole.

Semiconductor memory cells having common contact hole

Two trenches are formed at a predetermined distance on a main surface of a semiconductor substrate. An oxide film and a nitride film are successively formed on the main surface of the semiconductor including the inner surfaces of the trenches. After a resist is formed over the whole surface including the inner surfaces of the trenches, the resist is patterned to expose a portion of the nitride film on a side surface of each trench. The exposed portions of the nitride film are removed by using the patterned resist as a mask and thermal oxidation is applied. Then, an isolation oxide film is formed on a region between the trenches and an end of a bird's beak is located on a side surface of each trench and is connected to the oxide film formed in each trench.

Semiconductor device having an isolation oxide film

A semiconductor memory device comprises a semiconductor substrate, four memory cells arranged in point symmetry on the main surface, each of the memory cells having one transistor (6) formed around the point of symmetry and one capacitor adjacent to the outside of the transistor (6), the capacitor having a surface capacitor region (4a) parallel to the main surface and a trench capacitor region (40a) parallel to a side wall of a trench (40) formed in the main surface along the outer periphery of the surface capacitor region (4a), and an insulating layer (10) covering the memory cells and having one contact hole (2) arranged at the center of the point symmetry, with the contact hole (2) enabling electrical contact to each transistor (6).

Semiconductor memory device

A semiconductor memory device comprises four memory cells (4a, 6) arranged in point symmetry on a semiconductor substrate (1), and an insulating layer (10) covering the memory cells and having one contact hole (2) placed in the center of the point symmetry, with the contact hole enabling electrical connection to each of the memory cells.

A method for producing an impurity containing semiconductor substrate includes depositing an impurity on selected portions of the substrate by placing a charge on the substrate and converting a gaseous impurity containing atmosphere into a plasma. The impurity may then be diffused into the substrate to a controlled and shallow depth by employing a laser or the like to selectively irradiate the impurity.

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Hyogo, Japan

Masahiro Yoneda