Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Hitachi Ulsi Systems Co., Ltd.

Other

Elpida Memory, Inc.

Masahiro Moniwa

Kousuke Okuyama

Toshifumi Takeda

Yasushi Koubuchi

Youhei Yamada

Koichi Nagasawa

Hiraku Chakihara

Akio Nishida

Riichiro Takemura

Mitsuhiro Noguchi

Hideyuki Matsuoka

Makoto Mizuno

Keiji Okamoto

Tadanori Yoshida

Yasuhiko Takahshi

Yasuhiko Takahashi

ShinIchiro Kimura

Kiyonori Ohyu

Kenichi Kuroda

Nozomu Matsuzaki

Masayuki Kojima

Toru Kaga

Kozo Watanabe

Atsushi Ogishima

Terunori Warabisako

Dai Hisamoto

Syunichi Hashimoto

Nozomu Matsuda

Tomonori Sekiguchi

Hiroshi Miki

Norikatsu Takaura

Hideo Sunami

Hiroshi Kawakami

Yoshihisa Fujisaki

Atsushi Hiraiwa

Masanobu Miyao

Kazuyoshi Torii

Eiji Takeda

Kota Funayama

Kazuo Nakazato

Hiroshi Kujirai

Keiko Kushida

Fumihiko Nitta

Satoshi Iida

Masamichi Matsuoka

Tsuyoshi Tabata

Haruhiko Tanaka

Shoji Shukuri

Tokuo Kure

Makoto Ohkura

Kikuo Kusukawa

Satoru Haga

Teruo Kisu, Legal Representative

Haruko Kisu, Legal Representative

Kenichi Osada

Hiroyuki Ohta

Akihiro Shimizu

Eiichi Murakami

Akira Kotabe

Yasuo Wada

Nobuyoshi Natsuaki

Keizo Kawakita

Shiro Kamohara

Yasuhiko Kawashima

Masao Tamura

Yukihiro Kumagai

Shingo Nasu

Hiroyasu Ishizuka

Tadashi Suzuki

Yuuichi Madokoro

Chiemi Hashimoto

Teruo Kisu

Haruko Kisu

A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

Semiconductor memory device and a method of manufacturing the same

A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.

Semiconductor device and method of manufacturing the same

Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device

Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Semiconductor integrated circuit device

Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.

A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element. Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.

Interconnections are formed over an interlayer insulating film which covers MISFETQformed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Growing community of inventors

Sayama, Japan

Masahiro Moniwa