Fujitsu Corporation

Masahiko Takikawa

Toshihide Kikkawa

Kozo Makiyama

Yuji Awano

Satoru Asai

Yusuke Matsukura

Naoki Hara

Yasunori Tateno

Masaki Nagahara

Shuichi Tanaka

Tadao Okabe

A carrier transfer layer of compound semiconductor material is disposed on or over a support substrate, and a gate electrode of conductive material is disposed on or over the carrier transfer layer at a partial region thereof. A cap layer of non-doped compound semiconductor material is disposed on or over the carrier transfer layer at both sides of the gate electrode. The thickness of the cap layer is 100 nm or thicker. two current electrodes are formed in ohmic contact with the carrier transfer layer. An enhancement mode MESFET is provided whose gain and output power are suppressed from being lowered.

Enhancement type MESFET

A semiconductor device comprises a GaAs substrate 10; a buffer layer 12 formed on the GaAs substrate 10 and having a wider band gap than that of InGaP; a channel layer 14 formed on the buffer layer 12 and formed of an InGaP; a gate electrode 34 for controlling current of the channel layer 14. InGaP has a high carrier mobility and large .GAMMA.-L energy difference. Accordingly, the channel layer is formed of InGaP, whereby the semiconductor device which is operable at high speed and high voltage can be obtained.

Semiconductor device with InGaP channel layer

A field-effect transistor including a channel layer, a source electrode, a drain electrode, a high-resistance layer provided on the channel layer between the source electrode and the drain electrode and a gate electrode provided in an opening formed in the high-resistance layer, wherein the high-resistance layer is defined by a first side-wall facing the source electrode and a second side-wall facing the drain electrode, such that the first side-wall is separated from the source electrode.

Field effect semiconductor device having a reduced leakage current

A method of fabricating a compound semiconductor device includes a step of removing a semiconductor layer by an etching process to expose an upper major surface of an underlying semiconductor layer, followed by a growth of another semiconductor layer of the p-type on the surface thus exposed, wherein the exposed surface is cleaned by a flushing of a gaseous metal organic compound containing a group V element for removing impurities therefrom and further doping the exposed surface to the p-type.

Semiconductor device having a regrowth crystal region

A HEMT type semiconductor device includes a semiconductor substrate, a buffer semiconductor layer formed on the substrate, a first semiconductor well layer formed on the buffer layer and serving as a first conductivity type channel layer, a second semiconductor well layer formed on the first well layer and serving as a second conductivity type opposite the first conductivity, a channel layer and a potential barrier layer formed on the second well layer and forming a potential barrier for carriers. The substrate is made of GaAs or InP, and the layers are successively and epitaxially grown on the substrate. A two dimensional hole gas and a two dimensional electron gas are confined in the first well layer and in the second well layer, respectively.

HEMT type semiconductor device having two semiconductor well layers

A semiconductor device includes an InP substrate, an intrinsic InGaAs channel layer formed on the InP substrate and lattice matched to the InP substrate, a doped GaAsSb carrier supply layer formed on the intrinsic InGaAs channel layer and lattice matched to the InP substrate, a gate electrode formed on the doped GaAsSb carrier supply layer, and a source electrode and a drain electrode which are respectively formed on the doped GaAsSb carrier supply layer and located on both sides of the gate electrode.

Semiconductor device and production method thereof

A semiconductor device having a selectively doped heterostructure comprises a substrate, a channel layer, a carrier supplying layer, and electrodes provided on the carrier supplying layer. The channel layer and the carrier supplying layer form a heterojunction interface at a boundary between the channel layer and the carrier supplying layer with a two-dimensional electron gas formed in the channel layer along the heterojunction interface. The carrier supplying layer and the channel layer have respective compositions determined such that the .GAMMA. valley of the conduction band of the carrier supplying layer has an energetical level higher than a corresponding energetical level of the .GAMMA. valley of the conduction band of the channel layer at the heterojunction interface, the L valley of the conduction band of the carrier supplying layer has an energetical level higher than a corresponding energetical level of the L valley of the conduction band of the channel layer at the heterojunction interface, the X valley of the conduction band of the carrier supplying layer has an energetical level higher than a corresponding energetical level of the X valley of the conduction band at the heterojunction interface, the energetical level of the .GAMMA. valley of the conduction band of the carrier supplying layer is equal to or higher than the energetical level of the L valley of the conduction band of the channel layer at the heterojunction interface, and the energetical level of the L valley of the conduction band of the carrier supplying layer is equal to or higher than the energetical level of the X valley of the conduction band of the channel layer at the heterojunction interface.

Semiconductor device having a selectively doped heterostructure

A method for fabricating a compound semiconductor device having a semi-insulating layer of a group III-V compound semiconductor material that contains arsenic as a group V element. The method includes a step of growing the semi-insulating layer from a source gas of the group V element that contains both arsine and an organic compound of arsenic, wherein arsine and the organic compound of arsenic are used simultaneously with a mixing ratio to achieve a desired high resistivity in the semi-insulating layer.

Method for fabricating a semiconductor device including a

Method of producing a semiconductor device

A high electron mobility transistor comprises a semiinsulating substrate, an undoped channel layer formed on the semiinsulating substrate and made of undoped gallium arsenide (GaAs), a doped carrier supplying layer formed on the undoped channel layer and made of a II-VI family compound semiconductor having an electron affinity smaller than that of the undoped gallium arsenide and having an energy gap greater than that of the undoped gallium arsenide, and source, drain and gate electrodes formed on the doped carrier supplying layer.

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Yokohama, Japan

Masahiko Takikawa