Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Masahiko Hiratani

Yuichi Matsui

Yasuhiro Shimamoto

Toshihide Nabatame

Shinpei Iijima

Yoshitaka Nakamura

Hiroshi Miki

Takao Watanabe

Satoru Akiyama

Kazumasa Takagi

Tomoyuki Hamada

Yuzuru Ohji

Kazuyoshi Torii

Tokuumi Fukazawa

Katsuki Miyauchi

Naruhiko Nakanishi

Hiroyuki Ohta

Shinichiro Kimura

Toshikazu Nishino

Kazuo Nojiri

Takashi Yunogami

Yoshinobu Tarutani

Sukeyoshi Tsunekawa

Keiko Kushida

Yukihiro Kumagai

Yasuhiro Sugawara

Masato Kunitomo

Misuzu Kanai

Yuzuru Oji

Katsunori Obata

Satoshi Yamamoto

Yukio Ito

Yoshimi Kawanami

Masaaki Futamoto

Yukio Honda

Fumiyoshi Kirino

Ushio Kawabe

Yoshihisa Fujisaki

Toshiyuki Aida

Shinichiro Takatani

Tetsuichi Kudo

Hiroshi Sakuma

Haruhiro Hasegawa

Akira Tsukamoto

Keiichi Kanehori

Mitsuo Suga

Toshio Ando

Yuuichi Madokoro

Kazushige Imagawa

Yuuichi Matsui

Tsuyoshi Seko

Shin'ichiro Saitoh

Shinichiroh Saitoh

Uki Kabasawa

A memory cell capacitor (C) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same

The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600&#xb0; C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

Capacitive electrode having semiconductor layers with an interface of separated grain boundaries

Semiconductor device having plural dram memory cells and a logic circuit

The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600&#xb0; C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of a niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

A ruthenium electrode with a low amount of oxygen contamination and high thermal stability is formed by a chemical vapor deposition method. In the chemical vapor deposition method using an organoruthenium compound as a precursor, the introduction of an oxidation gas is limited to when the precursor is supplying, and the reaction is allowed to occur at a low oxygen partial pressure. Consequently, it is possible to form a ruthenium film with a low amount of oxygen contamination. Further, after formation of the ruthenium film, annealing at not less than the formation temperature is performed, thereby forming a ruthenium film with high thermal stability.

Fabricating method of semiconductor integrated circuits

In a method for manufacturing an FET having a gate insulation film with an SiOequivalent thickness of 2 nm or more and capable of suppressing the leak current to 1/100 or less compared with existent SiOfilms, an SiOfilm of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiOfilm is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Semiconductor device and manufacturing method thereof

A process for forming the lower and upper electrodes of a high dielectric constant capacitor in a semiconductor device from an organoruthenium compound by chemical vapor deposition. This chemical vapor deposition technique employs an organoruthenium compound, an oxidizing gas, and a gas (such as argon) which is hardly adsorbed to the ruthenium surface or a gas (such as ethylene) which is readily adsorbed to the ruthenium surface. This process efficiently forms a ruthenium film with good conformality in a semiconductor device.

Fabrication method for semiconductor integrated devices

In the method of manufacturing a semiconductor device according to this invention, when an interlayer insulating film is fabricated such that an opening is cylindrical and low-pressure and long-throw sputtering is used for forming a lower ruthenium electrode, a ruthenium film can be deposited on the side wall of a deep hole. Further, after removing the ruthenium film deposited on the upper surface of the interlayer insulating film, a dielectric material comprising, for example, a tantalum pentoxide film is deposited. Successively, an upper ruthenium electrode is deposited using, for example, Ru(EtCp)as a starting material and by chemical vapor deposition of conveying the starting material by bubbling. The upper ruthenium electrode can be formed with good coverage by using conditions that the deposition rate of the ruthenium film depends on the formation temperature (reaction controlling condition). This invention can provide a fine concave type capacitor having a ruthenium electrode.

Method for manufacturing a ruthenium film for a semiconductor device

Method of making a memory structure having a multilayered contact and a storage capacitor with a composite dielectric layer of crystalized niobium pentoxide and tantalum pentoxide films

By using a solid solution of tantalum pentoxide and niobium pentoxide as a dielectric film installed between upper electrode and lower electrode in a capacitor which is used in a semiconductor device, the capacitor structure can be simplified to improve reliability of the semiconductor device while reducing the production cost thereof.

Semiconductor device and method of manufacturing thereof

The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600&deg; C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of a niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

Semiconductor device

In a method for manufacturing an FET having a gate insulation film with an SiO equivalent thickness of 2 nm or more and capable of suppressing the leak current to {fraction (1/100)} or less compared with existent SiO films, an SiO film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Growing community of inventors

Akishima, Japan

Masahiko Hiratani