Spansion Llc.

Fujitsu Amd Semiconductor Limited

Masahiko Higashi

Yukihiro Utsuno

Hiroyuki Nansei

Tatsuya Kajita

Hideo Takagi

Kentaro Sera

Manabu Nakamura

Hiroshi Murai

Kenichi Fujii

Naofumi Takahata

Naoki Takeguchi

Hiroaki Kouketsu

A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by implanting ions into the sidewall of SiN.

Semiconductor device and method of fabrication

Methods and structures for discharging plasma formed during the fabrication of semiconductor device are disclosed. The semiconductor device includes a wordline, a common ground line and a fuse structure for electrically coupling the wordline and the common ground line until a break signal is applied via the fuse structure.

Methods and structures for discharging plasma formed during the fabrication of semiconductor device

A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.

Fabricating method of mirror bit memory device having split ONO film with top oxide film formed by oxidation process

A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated.

Flash memory device with word lines of uniform width and method for manufacturing thereof

There are provided a semiconductor device and a fabrication method therefor including an ONO film () formed on a semiconductor substrate (), a word line () formed on the ONO film (), a bit line () formed in the semiconductor substrate (), and a conductive layer () that is in contact with the bit line (), runs in a length direction of the bit line (), and includes a polysilicon layer or a metal layer. In accordance with the present invention, a semiconductor device and a fabrication method therefor are provided wherein degradation of the writing and erasing characteristics and degradation of the transistor characteristics such as a junction leakage are suppressed, and the bit line resistance is decreased.

Fabrication method for semiconductor device having laminated electronic conductor on bit line

A method for manufacturing a semiconductor device which includes steps of forming a dummy layer on a semiconductor substrate, forming a groove 12 in the semiconductor substrate while using the dummy layer as a mask, forming a tunnel insulating film and a trap layer to cover an inner surface of the groove and the dummy layer, eliminating the trap layer formed above the upper surface and at the sides of the dummy layer, and forming a top insulating film to cover a remaining trap layer and the exposed tunnel insulating film.

Method for manufacturing SONOS flash memory

The present invention relates to a semiconductor device that includes a semiconductor substrate () having source/drain diffusion regions () formed therein and control gates () formed thereon, with grooves () being formed on the surface of the semiconductor substrate () and being located below the control gates () and between the source/drain diffusion regions (). The grooves () are separated from the source/drain diffusion regions (), thereby increasing the effective channel length to maintain a constant channel length for charge accumulation while enabling the manufacture of smaller memory cells. The present invention also provides a method of manufacturing the semiconductor device.

Semiconductor device and method of manufacturing the same

Semiconductor device having laminated electronic conductor on bit line

The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes bit lines disposed in a semiconductor substrate, a first ONO disposed between the bit lines on the semiconductor substrate, and a second ONO film disposed on each of the bit lines. The film thickness of a first silicon nitride film in the first ONO film is larger than the film thickness of a second silicon nitride film in the second ONO film.

Sonos device with insulating storage layer and P-N junction isolation

A semiconductor memory includes first and second source regions that are formed in a semiconductor substrate and run in orthogonal directions. The first and second source regions are diffused regions and are electrically connected to each other at crossing portions thereof. The semiconductor device may further include drain regions formed in the semiconductor substrate, bit lines that run in the direction in which the second source region runs, and a source line formed above the second source region, wherein a contact between the source line and the second source region is aligned with contacts between the bit lines and drain regions formed in the semiconductor substrate.

Semiconductor memory and method of fabricating the same

A semiconductor device is provided which includes a gate electrode () provided on a semiconductor substrate (), an oxide/nitride/oxide (ONO) film () that is formed between the gate electrode () and the semiconductor substrate () and has a charge storage region () under the gate electrode (), and a bit line () that is buried in the semiconductor substrate () and includes a low concentration diffusion region (), a high concentration diffusion region () that is formed in the center of the low concentration diffusion region () and has a higher impurity concentration than the low concentration region, a source region, and a drain region. The semiconductor device can improve the source-drain breakdown voltage of the transistor while suppressing fluctuation of electrical characteristics or junction current between the bit line () and the semiconductor substrate ().

Growing community of inventors

Aizuwakamatsu, Japan

Masahiko Higashi