Kabushiki Kaisha Toshiba

Kabushiki Kaihsa Toshiba

Masahiko Hasunuma

Hisashi Kaneko

Sachiyo Ito

Atsuko Sakata

Junichi Wada

Hiroshi Toyoda

Tomio Katata

Nobuo Hayasaka

Katsuya Okumura

Takashi Kawakubo

Naofumi Nakamura

Takamasa Usui

Seiichi Omoto

Soichi Yamashita

Takashi Kawanoue

Masaki Yamada

Kazuyuki Higashi

Akihiro Kajita

Hideki Shibata

Masaaki Hatano

Kazuya Kinoshita

Kazuhiko Itaya

Kazuhide Abe

Michihiko Nishigaki

Toshihiko Nagano

Ryoichi Ohara

Takaaki Yasumoto

Kenya Sano

Naoko Yanase

Hironobu Shibata

Hiroshi Tomita

Haruo Okano

Rempei Nakata

Hideshi Miyajima

Atsuhito Sawabe

Shuichi Komatsu

Mitsuhiro Nakao

Akitsugu Hatazaki

Keizo Shimamura

Toshiaki Komukai

Junsei Tsutsumi

Masami Miyauchi

Kaoru Tada

Shohei Shima

Yoshiko Kohanawa

Soichi Inoue

Masamitsu Itoh

Takeshi Ishizaki

Noriaki Matsunaga

Miyoko Shimada

Masami Aoki

Yasuyuki Sonoda

Mituo Kawai

Takeshi Nishioka

Sachiko Kobayashi

Kazuko Yamamoto

Hideto Matsuyama

Jun-ichi Wada

Mitsuo Kawai

Tetsuo Fujiwara

Yuji Yasuda

Noriyuki Chujyo

According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap layer provided on the upper surface of the interconnect, and a barrier film provided between the interconnect and a second interlayer insulating film covering the interconnect. The interconnect includes a high-melting-point conductive layer, and the width of the interconnect is smaller than the width of the cap layer. The barrier film includes a compound of a contained element in the high-melting-point conductive layer.

Semiconductor device and semiconductor device manufacturing method

A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.

Semiconductor device having oxidized metal film and manufacture method of the same

An embodiment of the present invention provides a method for manufacturing a semiconductor device. This method comprises: forming a seed film at least on an inner face of a recessed portion of a substrate; forming a protection film on the seed film, the protection film being made of a material that is more easily oxidized than a material forming the seed film; heat-treating the protection film; exposing at least part of the seed film by removing at least part of the heat-treated protection film; forming a plating film on the seed film through electrolytic plating to be buried in the recessed portion, by supplying current to the seed film that is at least partially exposed; and removing the plating film except for a portion buried in the recessed portion.

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a first metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, oxidizing at least part of the first metal film with oxidizing species remaining in the insulating film, and forming a second metal film, which includes any of a high melting point metal and a noble metal, on the first metal film, the first metal film and the second metal film sharing different metallic material.

A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.

Stress analysis method, wiring structure design method, program, and semiconductor device production method

A semiconductor device including at least two layers of interlayer-insulator-films stacked above a substrate and at least partially formed by a low-relative-dielectric-constant-film having a relative-dielectric-constant of 3.4 or less respectively, a plurality of wirings provided at least one within each of the interlayer-insulator-film and at least partially located within the low-relative-dielectric-constant-films, a plurality of plugs provided at least one within each of the interlayer-insulator-film and connected to a lower part of the wirings, and a plurality of reinforcement members provided at least one within each of the interlayer-insulator-film with being separated from the wirings at a predetermined interval, electrically cut from the wirings and the plugs, and at least partially located within the low-relative-dielectric-constant-films, and wherein, the interlayer-insulator-films, the wirings, the plugs, and the reinforcement members satisfy a predetermined relation for each of the interlayer-insulator-film.

Semiconductor device

A piezoelectric thin film device includes an amorphous metal film disposed on a substrate and a piezoelectric film disposed on the amorphous metal. One of crystal axis of the piezoelectric film is aligned in a direction perpendicular to a surface of the amorphous metal.

Piezoelectric thin film device and method for manufacturing the same

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

Semiconductor device including an insulating film and insulating pillars and manufacturing method of the semiconductor device

A method for fabricating a semiconductor device, includes forming a first dielectric film above a substrate, forming an opening in the first dielectric film, forming a catalytic characteristic film using at least one of a metal having catalytic characteristics and a conductive oxide having catalytic characteristics as its material on sidewalls and at a bottom of the opening, depositing a conductive material film using a conductive material in the opening in which the catalytic characteristic film is formed on the sidewalls and at the bottom, removing the catalytic characteristic film formed on the sidewalls of the opening, and forming a second dielectric film above the first dielectric film and the conductive material film after the removing.

Method for fabricating semiconductor device

A method for manufacturing a semiconductor device includes forming, on a substrate having a recessed portion on a surface, a plating film which is at least buried in the recessed portion and has a higher impurity concentration in an upper portion than in a lower portion, thermally treating the plating film, and removing the thermally treated plating film except for a portion buried in the recessed portion.

Interconnect metallization method having thermally treated copper plate film with reduced micro-voids

A semiconductor device includes an effective wire formed above a substrate in a multilayer interconnection structure and having a first electrode pad in a top layer; a first reinforcing material formed in the multilayer interconnection structure like surrounding the effective wire; a protective film configured to protect a final surface of the multilayer interconnection structure; and a second reinforcing material formed at a position in contact with the protective film and also between an area in which the effective wire is formed and a chip area end, the second reinforcing material being constituted by a film pattern whose Young's modulus is larger than that of a conductor constituting the first electrode pad and that of a conductor constituting the first reinforcing material.

A semiconductor device includes a first insulating layer provided above a semiconductor substrate. The first insulating layer includes a layer consisting essentially of a material having a relative dielectric constant smaller than 3. The first insulating layer includes a first integral structure consisting of a plug and wiring. The upper surface of the wiring is flush with the upper surface of the first insulating layer, and the lower surface of the plug is flush with the lower surface of the first insulating layer. A region protective member is formed of a second integral structure consisting of a plug and wiring. The second integral structure extends from the upper surface of the first insulating layer to the lower surface of the first insulating layer. The region protective member surrounds one of first to n-th regions (n being a natural 2 or more) partitioned by a boundary region on a horizontal plane.

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Yokohama, Japan

Masahiko Hasunuma