Sanyo Electric Co., Ltd.

Other

Masaaki Momen

Nobuyuki Sekikawa

Wataru Andoh

Suichi Kikuchi

Shuichi Kikuchi

Koichi Hirata

Masaaki Anezaki

Eiji Nishibe

Masafumi Uehara

Shinya Enomoto

A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layersuperimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness tof the gate electrodeon the second gate oxide filmsA andB is thinner than the thickness tof the prior art. Therefore, the height gap hbetween the gate electrodeand the N+type source layerand the height gap hbetween the gate electrodeand the N+type drain layerbecome smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film

Method of manufacturing insulated gate semiconductor device

The semiconductor device of this invention has a P type well region formed inside a P type semiconductor substrate, on which at least three gate insulating films each having a different thickness are formed. Also, the device has the gate electrode formed extending over the three gate insulating films. The ion implantation of the impurity for controlling the threshold voltage is performed only under the thinnest gate insulating film of the three gate insulating films.

Semiconductor device and manufacturing method thereof

A transistor of a semiconductor device has an increased driving capacity. The semiconductor device has a first gate insulation film formed by a selective oxidation, a second gate insulation film formed by thermal oxidation and a gate electrode formed across the first and the second gate insulation films. The second gate insulation film is composed of a thicker gate insulation film and a thinner gate insulation film.

Method of manufacturing semiconductor device

This invention is directed to the reduction of voltage dependence and thus allows easy design of integrated semiconductor circuits. The device is equipped with a P&#x2212; type resistance layer, in which a first voltage is applied to one end and a second voltage is applied to the other end and which is formed on the surface of an N-well region on the semiconductor substrate, a thin oxide film on the resistance layer, and a resistance bias electrode which includes the silicon layer formed on the thin oxide film. By adjusting the voltage applied to the resistance bias electrode, the voltage dependence of the resistance of the resistance layer is reduced.

Semiconductor device manufacturing method

A manufacturing method of this invention has an ion-implantation process for threshold voltage adjustment of an MOS transistor, including a process to form a first well of an opposite conductivity type in a substrate of one conductivity type, to form a second well of the opposite conductivity type having higher impurity concentration than that in the first well, under a region where a thin gate insulation film is formed, to form gate insulation films on the first well and the second well, each having a different thickness, to ion-implant first impurities of the one conductivity type into the wells of the opposite conductivity type under the condition that the impurities penetrate the gate insulation films of different thicknesses and to ion-implant second impurities of the one conductivity type into the second well of the opposite conductivity type under the condition that the second impurities penetrate the thin gate insulation film but do not penetrate the thick gate insulation film. Thus the ion-implantation process for the threshold voltage adjustment of a semiconductor device having gate insulation films of different thicknesses can be rationalized with this invention.

Manufacturing method of semiconductor device

A die size is reduced in a semiconductor device which has a gate electrode formed on a first gate insulation film and a second gate insulation film, source and drain regions (N&minus; layers and N&plus; layers) formed adjacent to the gate electrode and a channel region, wherein at least the gate electrode, the channel region and the source and drain regions are polygonal in shape.

Semiconductor device

A die size is reduced in a semiconductor device having a gate electrode formed on a first gate insulation film and a second gate insulation film, source and drain regions (N&minus; layers and N&plus; layers) formed adjacent to the gate electrode and a channel region, wherein the gate electrode, the channel region and the source and drain regions are hexagonal. Neighboring transistors are displaced from each other by a predetermined distance.

Polygonal structure semiconductor device

When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.

A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t of the gate electrode on the second gate oxide films A and B is thinner than the thickness t of the prior art. Therefore, the height gap h between the gate electrode and the N &plus; type source layer and the height gap h between the gate electrode and the N &plus; type drain layer become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film

Insulated gate semiconductor device and its manufacturing method

A semiconductor device having a P type well region formed inside a P type semiconductor substrate, on which at least three gate insulating films each having a different thickness are formed. Also, the device has the gate electrode formed extending over the three gate insulating films. The ion implantation of the impurity for controlling the threshold voltage is performed only under the thinnest gate insulating film of the three gate insulating films.

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Ojiya, Japan

Masaaki Momen