Renesas Technology Corp.

Hitachi-High-Technologies Corporation

Hitachi Electronics Engineering Co., Ltd.

Masaaki Mochiduki

Yuji Wada

Takeshi Wada

Hideyuki Aoki

Masaaki Namba

Noboru Uchida

Kaoru Fukuda

Shigeki Katsumi

Yoshio Kamiko

A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer (PC). The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out form the measurement PC unit; a plurality of performance boards (PFBs) mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations. The PC tester is adapted to take out the signal from the chipset LSI (large scale integrated circuit) on the PC mother board in the measurement PC unit to the individual memories on the memory module or the memory module per se and test them in quasi-operating conditions.

Method and apparatus for testing a memory device in quasi-operating conditions

Main tester unit tests an IC device for presence of a defect for each of a plurality of addresses of the IC device under predetermined test conditions and stores test results for the individual addresses into a first memory. Curing analysis processing section cures each of the addresses of the IC device determined as defective, on the basis of the test results for the individual addresses stored in the first memory. To this end, the curing analysis processing section may rearrange an address logic of the IC device to replace a physical space of the defective addresses with an extra or redundant address space and thereby place each of the defective addresses in a usable condition. In parallel with the operations by the curing analysis processing section, a defect analysis section acquires, from the main tester unit, the test results for the individual addresses along with data indicative of the predetermined test conditions for storage into a second memory, and analyzes a specific cause of the defect in the IC device on the basis of the stored data in the second memory. With this arrangement, it is possible to acquire information necessary for analyzing the defect in the IC during a curability determining analysis test on a mass production line and thereby can effectively analyze the specific cause of the detected defect.

IC testing apparatus and method

Growing community of inventors

Honjo, Japan

Masaaki Mochiduki