Kabushiki Kaisha Toshiba

Masaaki Kisou

Motohiko Takeuchi

Kenji Shimoda

Hisaharu Takeuchi

Shinji Yoda

Kazumasa Ikeda

Image track display apparatus including a memory for delaying an image signal by at least one vertical scanning period, a first subtraction circuit for taking a first difference signal between the image signal and its delayed image signal through the memory. The first difference signal includes first and second polarity components, a non-linear processing circuit for multiplying the one polarity component of the first difference signal by K times (0&lt;K&lt;1) and for reducing the other polarity component of the first difference signal to the zero value when the other polarity component exceeds a prescribed value, a second subtraction circuit for taking a second difference signal between the output signal of the non-linear processing circuit and the image signal, and a display device for displaying the delayed image signal obtained through the memory circuit.

Image track display apparatus

A circuit for reducing noises of a chrominance signal in a television receiver. The circuit includes a decoder for decoding first and second color difference signals, each including a noise component from a received chrominance signal, a signal subtraction circuit for generating a first frame difference signal in response to two successive first color difference signals and a second frame difference signal in response to two successive second color difference signals, a signal converting circuit for extracting a first compensation signal from the first frame difference signal and a second compensation signal from the second frame difference signal, a noise reduction circuit for reducing noises from the color difference signals in response to the compensation signals, a discrimination circuit for discriminating whether both the first and second frame difference signals are smaller than a prescribed level or not and for generating a control signal in response thereto, and a signal transmission circuit for transferring the compensation signals from the signal converting circuit to the noise reduction circuit in response to the control signal only when both the frame difference signals are smaller than the prescribed level.

Noise reduction circuit for a chrominance signal of a using frame

A noise reduction circuit stores the video signal of one frame as input through an A/D converter from a VTR main body, into a frame memory via a first subtracting circuit. A second subtracting circuit subtracts the delayed video signal delayed one frame, which is derived from said frame memory, from the video signal. The same outputs the subtraction result as a difference signal. The amplitude level of the video signal is detected by the detecting circuit. The nonlinear characteristic appropriate to the difference signal output from the subtracting circuit is selected by the level signal output from the detecting circuit. Subtracting circuit subtracts the noise component selected and extracted by the nonlinear processing circuit from the video signal, thereby to remove the noise component. The video signal with no noise component is applied through a D/A converter from the subtracting circuit, to a CRT display where it is visualized.

Noise reduction circuit for video signal having suitable nonlinear

A noise reduction circuit allows a field memory to store 1-field data of a video signal through a subtracting circuit. The video signal is supplied from a VTR through an A/D converter. The noise reduction circuit causes a subtracting circuit to subtract a delayed video signal, which is supplied from the field memory with a 1-field time delay, from the video signal and allows the resultant signal to be output as a field difference signal. A noise component included in the video signal is extracted by a noise extracting circuit in accordance with the field difference signal, and is output to the subtracting circuit. In a comparing circuit, the noise component is compared with a predetermined reference value so as to determine whether the video signal represents a motion or motionless picture. In accordance with this determination result, memory control circuit controls whether to write the video signal supplied from the subtracting circuit in the field memory. In addition, a video signal from which the noise component is removed is supplied from the subtracting circuit and monitored on a CRT display through a D/A converter or the like.

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Chiba, Japan

Masaaki Kisou