Other

Advanced Micro Devices Corporation

Fujitsu Corporation

Advance Micro Devices, Inc.

Fujitsu Amd Semiconductor Limited

Masaaki Higashitani

Hao Fang

John JianShi Wang

Narbeh Derhacobian

Michael K Templeton

Richard M Fastow

Mark W Randolph

Michael Allen Van Buskirk

Pau-Ling Chen

Timothy J Thurgate

Shane Charles Hollmer

Yue-Song He

Daniel Sobek

Kent Kuohua Chang

Carl Robert Huster

Kelwin Ko

K Michael Han

Maria Chow-Chan

Toru Ishigaki

Bill Cox

A method of fabricating nitride read-only memory (NROM) cells and arrays. The memory device is formed on a substrate. Each memory cell comprises a pair of bit lines extending in a first direction across the substrate, a pair of bit line dielectrics overlaying and covering the pair of bit lines, a charge-trapping layer formed over the channel region between the pair of bit lines, and a conductive connecting block formed on the charge-trapping layer. The charge-trapping layer comprising two oxide-nitride-oxide (ONO) structures separated by a gate oxide layer, where each ONO structures comprises a layer of nitride sandwiched between a bottom oxide layer and a top oxide layer. A plurality of straight, parallel-edged word lines extend across the substrate in a second direction and cross over the bit lines and channel regions. Each word line comprises a conductive material and is separated from the substrate by the conductive connecting blocks and bit lines dielectrics.

NROM cell with N-less channel

A system and method detecting the presence of polysilicon stringers on a memory array using a polysilicon stringer monitor. The polysilicon stringer monitor includes a continuous type-2 layer of polysilicon forming a first row and a second row across the active region and covering the active region in-between the first and second rows. The polysilicon stringer monitor further includes a continuous type-1 layer of polysilicon extending under the first row, wherein the type-1 layer also covers the active area in-between the first and second rows as well as covers the active area under the second row.

Method and system for providing a polysilicon stringer monitor

An non-volatile read only memory transistor for use in a memory array is disclosed. The non-volatile read only memory transistor features a substantially vertically oriented channel fabricated in a trench formed in the substrate. The channel length is dependent upon the depth of the trench and therefore a dense array of NROM transistors can be formed without adversely affecting the channel length and therefore the operational performance of the transistor.

Sidewall NROM and method of manufacture thereof for non-volatile memory cells

A semiconductor device having reduced field oxide recess and method of fabrication is disclosed. The method of fabricating the semiconductor device begins by performing an HF dip process on a substrate after field oxidation followed by performing a select gate oxidation. Thereafter, a core implant and a field implant are performed. After the implants, a tunnel oxide mask is deposited. The select gate oxide is then etched in areas uncovered by the tunnel oxide mask, and tunnel oxidation is performed.

Semiconductor device having reduced field oxide recess and method of fabrication

The present invention provides a method and apparatus for providing a polysilicon type-1 ESD transistor in a flash memory chip. The method and apparatus include providing a select gate transistor that includes a gate, a floating gate, a medium doped junction, and a source and drain. The method and apparatus further include forming the source and drain by performing a lightly doped drain (LDD) mask and etch, performing a LDD spacer deposition and LDD spacer etch, and performing a N&plus; implant mask and a N&plus; implant.

Type-1 polysilicon electrostatic discharge transistors

A single tunnel gate oxidation process for fabricating NAND memory strings where the gate oxide of the select transistors and the floating gate memory transistors are fabricated in a single oxidation step is disclosed. The select gate transistors and the floating gate memory transistors have an oxide thickness of 85 &angst;-105 &angst;. For single tunnel gate approach, a careful selection of the medium doped source/drain region implant conditions is necessary for proper function of the NAND memory string. In one embodiment, the medium doped source/drain region is doped with Arsenic to a concentrations of 10  /cm .

Nand flash memory with specified gate oxide thickness

A submicron semiconductor device having a self-aligned channel stop implant region, and a method for fabricating the semiconductor device using a trim and etch is disclosed. The semiconductor device includes a plurality of active regions separated by insulating regions. The method for fabricating the device includes depositing a nitride over a substrate and selectively covering the active regions with a mask, wherein the mask extends beyond boundaries of the active regions to narrow the width of the insulating regions. Thereafter, a channel stop implant is performed to form channel stops. The mask is then trimmed to the boundaries of the active regions after formation of the channel stops, followed by etching the nitride in exposed areas of the mask. Field oxide is then grown in the insulating regions, whereby the field oxide is self-aligned to the channel stops.

Submicron semiconductor device having a self-aligned channel stop region and a method for fabricating the semiconductor device using a trim and etch

A process which includes forming trench structures ( ) in a substrate ( ) as part of both the STI isolation structure and the LOCOS/STI isolation structure. Thereafter, a field oxide ( ) is formed which simultaneously forms a portion of the STI isolation structure and a portion of the LOCOS/STI isolation structure. Consequently, three different isolation structures may be formed without requiring a substantial increase in the complexity or number of processing steps.

Shallow trench isolation process particularly suited for high voltage circuits

The method of fabricating the semi-conductor device includes forming a center dielectric region on a substrate. The center dielectric region has a first thickness and the substrate includes a first conductive material. Then, a first plurality of spacers is formed near the center dielectric region. A second conductive material is implanted into the substrate using the first plurality of spacers for alignment. The second conductive material form sources/drains the first plurality of spacers are then removed and a dielectric layer is formed over the substrate and the source/drain regions. The dielectric layer has a second thickness that is less than the first thickness. A second plurality of spacers is formed near the center dielectric region. The second plurality of spacers are conductive and have a third thickness that is substantially equal to the difference of the first and second thickness'. A gate dielectric layer is formed over the substrate, center dielectric region, and second plurality of spacers. Finally, a control gate layer is formed over the gate dielectric layer.

Two bit flash cell with two floating gate regions

A method (,) of forming a NAND type flash memory device includes the steps of forming an oxide layer (,) over a substrate (,) and forming a first conductive layer (,) over the oxide layer. The first conductive layer (,) is etched to form a gate structure (,) in a select gate transistor region (,) and a floating gate structure (,) in a memory cell region (,). A first insulating layer (,) is then formed over the memory cell region (,) and a second conductive layer (,) is formed over the first insulating layer (,). A word line (,) is patterned in the memory cell region (,) to form a control gate region and source and drain regions (,) are formed in the in the substrate (,) in a region adjacent the word line (,) and in a region adjacent the gate structure (,). A second insulating layer (,) is formed over both the select gate transistor region (,) and the memory cell region (,) and first and second contact openings are formed in the second insulating layer (,) down to the gate structure (,) and the control gate region, wherein a depth (X) through the second insulating layer (,) down to the gate structure (,) and down to the control gate region are approximately the same, thereby eliminating a substantial overetch of the gate structure contact opening.

Elimination of poly cap easy poly 1 contact for NAND product

An intermediate implant step is performed to optimize the performance of the transistors in the peripheral portion of a floating gate type memory integrated circuit. The polysilicon layer (Poly 1) that forms the floating gate in the respective floating gate type memory devices prevents penetration of the optimizing implant into the core region in which the floating gate memory devices are formed. This permits the optimization implant to be performed without the need for an additional mask, thus reducing costs and production time.

Low voltage junction and high voltage junction optimization for flash

This invention describes methods for producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties. The methods involve the deposition of a barrier layer over the periphery of the semiconductor chip to prevent the introduction of contaminating nitrogen atoms into the periphery during a nitridation step in the core region of the semiconductor chip. By preventing the contamination of the gate areas of the periphery, the gate oxide regions so produced have increased breakdown voltages and increased reliability. This invention describes methods for etching the barrier layers used to protect the periphery from tunnel oxide nitridation. Semiconductor devices made with the methods of this invention have longer expected lifetimes and can be manufactured with higher device density.

Barrier layer decreases nitrogen contamination of peripheral gate

A method (200) of forming a NAND type flash memory device includes the steps of forming an oxide layer (202) over a substrate (102) and forming a first conductive layer (106) over the oxide layer. The first conductive layer (106) is etched to form a gate structure (107) in a select gate transistor region (105) and a floating gate structure (106a, 106b) in a memory cell region (111). A first insulating layer (110) is then formed over the memory cell region (111) and a second conductive layer (112, 118) is formed over the first insulating layer (110). A word line (122) is patterned in the memory cell region (111) to form a control gate region and source and drain regions (130, 132) are formed in the substrate (102) in a region adjacent the word line (122) and in a region adjacent the gate structure (107). A second insulating layer (140) is formed over both the select gate transistor region (105) and the memory cell region (111) and first and second contact openings are formed in the second insulating layer (140) down to the gate structure (107) and the control gate region, wherein a depth (X) through the second insulating layer (140) down to the gate structure (107) and down to the control gate region are approximately the same, thereby eliminating a substantial overetch of the gate structure contact opening.

Growing community of inventors

Sunnyvale, CA, United States of America

Masaaki Higashitani