Sandisk Technologies Inc.

Sandisk Corporation

Sandisk 3d LLC

Sandick Technologies Inc.

Masaaki Higashitani

Peter Rabkin

Mohan Dunga

Tuan Duc Pham

Johann Alsmeier

Jayavel Pachamuthu

Yingda Dong

Deepanshu Dutta

James K Kai

Man Lung Mui

Ken Oowada

Fumiaki Toyama

George Matamis

Kwang-Ho Kim

Nima Mokhlesi

Jeffrey W Lutze

Takashi Whitney Orimoto

Yangyin Chen

Lin Hou

Chun-Ming Wang

Yan Li

Jian Feng Chen

Gerrit Jan Hemink

Yuki Mizutani

Henry Chien

Venkatesh Ramachandra

Kiyohiko Sakakibara

Raghuveer S Makala

Xiying Costa

Haibo Li

Cynthia Hsu

Yanli Zhang

Zhenming Zhou

Rahul Sharangpani

Yupin K Fong

Hiroyuki Kinoshita

Jun Wan

Akio Nishida

Shinji Sato

Koichi Matsuno

Chun-Hung Lai

Roy E Scheuerlein

Hiroyuki Ogawa

Xiang Yang

Klaus Florian Schuegraf

Luca Giovanni Fasoli

Fei Zhou

George Samachisa

Henry Chin

Vinod Robert Purayath

Dengtao Zhao

Seungpil Lee

Toru Miwa

Shih-Chung Lee

Murshed Chowdhury

Geoffrey Steven Gongwer

Guirong Liang

Naoki Takeguchi

Hiroki Yabe

Perumal Ratnam

Kensuke Yamaguchi

Fumitoshi Ito

Manabu Sakai

Koji Hashimoto

Sergey Anatolievich Gorobets

Christopher John Petti

Dana Lee

Jianmin Huang

Satoshi Tanaka

Jiahui Yuan

Steven Theodore Sprouse

Tong Zhang

Kikuko Sugimae

Adarsh Rajashekhar

Franz Kreupl

Masayuki Ichige

Zhixin Cui

Grishma Shah

Masanori Tsutsumi

Changyuan Chen

Tien-Chien Kuo

Bo Lei

Hua-Ling Cynthia Hsu

Abhijith Prakash

Alan Kalitsov

Peng Zhang

Uday Chandrasekhar

Jixin Yu

Satoshi Shimizu

Farookh Moogat

YenLung Li

Ramy Nashed Bassely Said

Masayuki Hiroi

Jongsun Sel

Fumitaka Amano

Sung-Yong Chung

Kota Funayama

Hisakazu Otoi

Alex Mak

Chun Ge

A method of forming a bonded assembly includes providing a first semiconductor die containing and first metallic bonding structures and a first dielectric capping layer containing openings and contacting distal horizontal surfaces of the first metallic bonding structures, providing a second semiconductor die containing second metallic bonding structures, disposing the second semiconductor die in contact with the first semiconductor die, and annealing the second semiconductor die in contact with the first semiconductor die such that a metallic material of at least one of the first metallic bonding structures and the second metallic bonding structures expands to fill the openings in the first dielectric capping layer to bond at least a first subset of the first metallic bonding structures to at least a first subset of the second metallic bonding structures.

Bonded assembly including interconnect-level bonding pads and methods of forming the same

A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

Three-dimensional nor array and method of making the same

A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer. The barrier layer may be a dielectric blocking barrier layer.

Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making the same

A three-dimensional memory device containing a plurality of levels of memory elements includes a memory film containing a layer stack that includes a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer, a semiconductor channel, and a control gate electrode.

Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof

A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

Methods and apparatuses for forming semiconductor devices containing tungsten layers using a tungsten growth suppressant

A memory device includes at least one instance of a unit layer stack including a source layer, a channel-containing layer that contains a semiconductor channel, and a drain layer that are stacked along a vertical direction over a substrate; a memory opening vertically extending through the at least one instance of the unit layer stack; and a memory opening fill structure located in the memory opening and including a control gate electrode and a memory film in contact with each instance of the semiconductor channel. The memory film includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer.

A bonded assembly includes a backside peripheral circuit, a memory die and a first logic die. The memory die includes a doped semiconductor material layer, a three-dimensional memory array, and memory-side metal interconnect structures and first memory-side bonding pads embedded in memory-side dielectric material layers. The first logic die includes a logic-side peripheral circuit including a first subset of logic devices configured to control operation of the three-dimensional memory array, logic-side dielectric material layers, and logic-side metal interconnect structures and first logic-side bonding pads that are bonded to a respective one of the first memory-side bonding pads. The backside peripheral circuit includes a second subset of the logic devices located on a second side of the doped semiconductor material layer.

Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same

A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.

Erase method for non-volatile memory with multiple tiers

To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

Modelling and prediction of virtual inline quality control in the production of memory devices

A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.

Bonded assembly containing different size opposing bonding pads and methods of forming the same

A memory device includes a ferroelectric semiconductor channel, a source region contacting a first portion of the ferroelectric semiconductor channel, a drain region located above the source region and contacting a second portion of the ferroelectric semiconductor channel located above the first portion, a word line, and a gate dielectric located between the word line and the ferroelectric semiconductor channel.

Memory device including a ferroelectric semiconductor channel and methods of forming the same

Virtual quality control interpolation and process feedback in the production of memory devices

A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film contains a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer.

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Cupertino, CA, United States of America

Masaaki Higashitani