Infineon Technologies Ag

International Business Machines Corporation

Infineon Technologies LLC

Martin Ostermayr

Thomas Nirschl

Peter Huber

Alexander Olbrich

Richard Lindsay

Sajan Marokkey

Jenny Lian

Yannick Martelloni

Klaus Herold

Ettore Amirante

Roberto Schiwon

Hans-Joachim Barth

Thomas Fischer

Henning Haffner

Uwe Paul Schroeder

Chandrasekhar Sarma

Winfried Kamp

Vincent Gouin

Siegmar Koeppe

Erwin Ruderer

Christophe Chanussot

Klaus Schrüfer

Gabriela Brase

Robert Chi-Foon Wong

Anton Huber

Chandraserhar Sarma

Ekkart Martin

A memory cell includes diffusion regions formed in a substrate. Each of the diffusion regions extends along a vertical direction in a layout view at a substrate level. A first gate electrode structure at a gate electrode level is generally dogleg shaped. The first gate electrode structure extends in an oblique direction, turns to a horizontal direction, extends over and crosses the diffusion regions in the horizontal direction. A first contact structure at a contact level is generally rectangular shaped in the layout view of the cell. The first contact structure electrically connects a first source/drain region of the first diffusion region to the first gate electrode structure and the first source/drain region of the second diffusion region. The first contact structure extends from the first source/drain region of the first diffusion region to the first source/drain region of the second diffusion region at the contact level.

SRAM memory cell having a dogleg shaped gate electrode structure

A system and a method for transistor level routing are disclosed. The method comprises forming a high-k dielectric layer over a substrate, forming a metal layer directly over the high-k dielectric layer, and selectively disposing a semiconductive layer over the metal layer. The method further comprises forming a first transistor in a first region and a second transistor in a second region spaced from the first region, the first and second transistor having gate stacks comprising a high-k dielectric layer, a metal layer and a semiconductive layer, and forming an electrical connection between the first transistor and the second transistor comprising the high-k dielectric layer and the metal layer but not the semiconductive layer.

Transistor level routing

Semiconductor devices, capacitors, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a capacitor includes forming a first material over a workpiece, and patterning the first material, forming a first capacitor plate in a first region of the workpiece and forming a first element in a second region of the workpiece. A second material is formed over the workpiece and over the patterned first material. The second material is patterned, forming a capacitor dielectric and a second capacitor plate in the first region of the workpiece over the first capacitor plate and forming a second element in a third region of the workpiece.

Capacitors and methods of manufacture thereof

In an embodiment, a method of operating a memory cell coupled to a first port and to a second port includes determining if a first port is requesting to access the memory cell and determining if a second port is requesting to access the memory cell. Based on the determining, if the first port and the second port are simultaneously requesting to access the memory cell, the second port is deactivated, the memory cell is accessed from the first port, and an accessed memory state is propagated from the first port to circuitry associated with the second port.

Semiconductor memory device and method

Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance.

Methods for forming contacts in semiconductor devices

In accordance with an embodiment of the present invention, a method for making a semiconductor device comprises forming a photo sensitive layer on a semiconductive substrate, and forming an L-shaped structure in the photo sensitive layer by exposing the photo sensitive layer to light via a reticle, wherein the reticle comprises an L-shapes feature having a first non-orthogonal edge at an intersection of two legs of the L-shaped feature.

L-shaped feature, method of making an L-shaped feature and method of making an L-shaped structure

Method and device for controlling a memory access and correspondingly configured semiconductor memory A method and a device for controlling a memory access of a memory comprising memory cells are described. A completion of the memory access is determined by means of at least one dummy bit line. The at least one dummy bit line is connected to a plurality of memory cells of the memory cells of the memory such that a content of the at least one memory cell can be read out via the at least one dummy bit line. The at least one memory cell can be set to a predetermined potential. Each of said plurality of memory cells is connected to the at least one dummy bit line and to at least one dummy word line such that each of said plurality of memory cells can be set to the predetermined potential by means of the at least one dummy bit line and by means of the at least one dummy word line.

Method and device for controlling a memory access and correspondingly configured semiconductor memory

System and method for transistor level routing is disclosed. A preferred embodiment comprises a semiconductor device including a first semiconductor device formed on a first active area in a substrate, the first semiconductor device having a first gate stack comprising a first high-k dielectric layer, a first metal layer and a first poly-silicon layer. The semiconductor device further includes a second semiconductor device formed on a second active area in the substrate, the second semiconductor device having a second gate stack comprising a second high-k dielectric layer, a second metal layer and a second poly-silicon layer. An electrical connection connects the first semiconductor device with the second semiconductor device and overlies the first active area, the second active area and a portion of the substrate between the first active area and the second active area. The electrical connection includes a high-k dielectric layer and a metal layer but not a poly-silicon layer and the metal layer is arranged directly over the high-k dielectric layer.

A system for terminating a homogenous cell array is disclosed. A preferred embodiment comprises a plurality of homogenous cells arranged in rows and columns to form the homogenous cell array, wherein a first homogenous cell of each column is electrically differently connected than a rest of the homogenous cells of the column.

Homogenous cell array

A semiconductor device and method of manufacturing thereof. The semiconductor device has at least one NMOS device and at least one PMOS device provided on a substrate. An electron channel of the NMOS device is aligned with a first direction. A hole channel of the PMOS device is aligned with a different second direction that forms an acute angle with respect to the first direction.

Semiconductor device and method for manufacturing the same

Implementations are presented herein that relate to a memory cell, a memory device, a device and a method of accessing a memory cell.

Memory cell, memory device, device and method of accessing a memory cell

Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a method of manufacturing a semiconductor device includes a exposing a first photo resist layer using a first light beam thereby forming first features. The first exposure is performed by the first light beam passing through a first dipole illuminator and then a first mask. A dipole axis of the first dipole illuminator is oriented in a first direction. After exposing the first photo resist layer, forming second features using a second exposure with a second light beam. The second exposure is performed by the second light beam passing through a second dipole illuminator and then a second mask. A dipole axis of the second dipole illuminator is oriented in a second direction. The first direction and the second direction are not perpendicular. The first and the second features comprise a pattern for forming contact holes.

Gridded contacts in semiconductor devices

A memory system and method are described. For example, a memory cell includes a capacitance and an access circuit in association with the capacitance and having an access circuit terminal. The memory cell further includes a voltage control unit to adjust a potential at the access circuit terminal in a retention state such that a retention time of the memory cell is increased. A method of operating a memory cell includes, for example, adjusting a potential at an access circuit terminal of the memory cell to increase a retention time.

Method of operating a memory cell, memory cell and memory unit

The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.

Growing community of inventors

Feldkirchen, Germany

Martin Ostermayr