Globalfoundries Inc.

Advanced Micro Devices Corporation

Martin Mazur

Ralf Richter

Joerg Hohage

Hans-Juergen Thees

Wolfram Grundke

Andy C Wei

Khoi A Phan

Kai Frohberg

Matthias Schaller

Jeffrey P Erhardt

Frank Seliger

Jerry Cheng

Daniel E Sutton

Richard J Bartlett

Anthony P Coniglio

Carol M Bradway

Peter Baars

Sven Beyer

Markus Lenski

Matthias Lehr

Uwe Griebenow

Klaus Hempel

Martin Gerhardt

Massud Aminpur

Carsten Hartig

Uwe Schulze

Heike Salz

Kerstin Ruttloff

Volker Grimm

Sven Mueller

Erik Geiss

Peter Krottenthaler

Ralf Otterbach

Steffen Laufer

Georg Sulzer

Andre Poock

Dietmar Henke

Roberto Klingler

Henke Dietmar

Jochen Klais

Andreas Becker

A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI substrate in a logic area of the SOI substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the SOI substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.

Semiconductor device comprising a floating gate flash memory device

In one example, a reticle disclosed herein includes a body having a center, an arrangement of a plurality of exposure patterns, wherein a center of the arrangement is offset from the center of the body, and at least one open feature defined on or through the body of the reticle. In another example, a method is disclosed that includes forming a layer of photoresist above a plurality of functional die and a plurality of incomplete die, exposing the photoresist material positioned above at least one of the functional die and/or at least one of the incomplete die, performing an incomplete die exposure processes via an open feature of the reticle to expose substantially all of the photoresist material positioned above the plurality of incomplete die, and developing the photoresist to remove the portions of the photoresist material positioned above the incomplete die.

Reticles for use in forming implant masking layers and methods of forming implant masking layers

When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.

Enhanced patterning uniformity of gate electrodes of a semiconductor device by late gate doping

Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.

Method of forming self-aligned contacts for a semiconductor device

When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing an upper portion of the final work function metal, for instance a titanium nitride material in P-channel transistors. In some illustrative embodiments, the selective removal of the metal-containing electrode material in an upper portion of the gate opening may be accomplished without unduly increasing overall process complexity.

High-k metal gate electrode structures formed by reducing a gate fill aspect ratio in replacement gate technology

In a replacement gate approach, the dielectric cap layers of the gate electrode structures are removed in a separate removal process, such as a plasma assisted etch process, in order to provide superior process conditions during the subsequent planarization of the interlayer dielectric material for exposing the sacrificial gate material. Due to the superior process conditions, the selective removal of the sacrificial gate material may be accomplished with enhanced uniformity, thereby also contributing to superior stability of transistor characteristics.

Cap layer removal in a high-K metal gate stack by using an etch process

By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.

Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device

When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.

Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning

By incorporating a material exhibiting a high adhesion on chamber walls of a process chamber during sputter etching, the defect rate in a patterning sequence on the basis of an ARC layer may be significantly reduced, since the adhesion material may be reliably exposed during a sputter preclean process. The corresponding adhesion layer may be positioned within the ARC layer stack so as to be reliably consumed, at least partially, while nevertheless providing the required optical characteristics. Hence, a low defect rate in combination with a high process efficiency may be achieved.

Arc layer having a reduced flaking tendency and a method of manufacturing the same

Mask defects, such as crystal growth defects and the like, may be efficiently detected and estimated at an early stage of their development by generating test images of the mask under consideration and inspecting the images on the basis of wafer inspection techniques in order to identify repeatedly occurring defects. In some illustrative embodiments, the exposure process for generating the mask images may be performed on the basis of different exposure parameters, such as exposure doses, in order to enhance the probability of detecting defects and also estimating the effect thereof depending on the varying exposure parameters. Consequently, increased reliability may be achieved compared to conventional direct mask inspection techniques.

Method of detecting repeating defects in lithography masks on the basis of test substrates exposed under varying conditions

By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device

An advanced process control (APC) architecture comprising a process model that incorporates a target offset term is provided. The APC architecture may be applied to a so-called develop inspect critical dimension (DICD) model using the target offset term to correct at least one exposure parameter on the occurrence of an abrupt event. A corresponding event may, for example, concern a modified reflectivity of processed substrates, for example due to a rework of substrates covered by amorphous carbon material.

Advanced process control model incorporating a target offset term

During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions more effective. Hence, the mechanical stress may be substantially induced by the contact etch step layer rather than by a combination of the spacer elements and the etch stop layer, thereby significantly facilitating the stress engineering in the channel region. By additionally performing a plasma treatment, different amounts of stress may be created in different transistor devices without unduly contributing to process complexity.

Technique for controlling mechanical stress in a channel region by spacer removal

By using conventional spacer and etch techniques, microstructure elements, such as lines and contact openings of integrated circuits, may be formed with dimensions that are mainly determined by the layer thickness of the spacer layer. In a sacrificial layer, an opening is formed by means of standard lithography and etch techniques and, subsequently, a spacer layer is conformally deposited, wherein a thickness of the spacer layer at the sidewalls of the opening substantially determines the effective width of the microstructure element to be formed. By using standard 193 nm lithography and etch processes, gate electrodes of 50 nm and beyond can be obtained without significant changes in standard process recipes.

Method of defining the dimensions of circuit elements by using spacer deposition techniques

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Pulsnitz, Germany

Martin Mazur