Mentor Graphics Corporation

Siemens Industry Software Gmbh

Other

Martin Keim

Ronald Press

Etienne Racine

Janusz Rajski

Gang Paul Chen

Manish Sharma

Nagesh Tamarapalli

Huaxing Tang

Jean-Francois Cote

Jongsin Yun

Wu-Tung Cheng

Yu Hu

Yu Jane Huang

Benoit Nadeau-Dostie

Ruifeng Guo

Liyang Lai

Jing Ye

Givargis Avareh Danialy

This application discloses a memory built-in self-test system to prompt a memory device to sense values of stored data using a reference trim during memory read operations. The memory built-in self-test system can automatically set the reference trim for the memory device. The memory built-in self-test system includes a memory built-in self-test controller to prompt the memory device to perform the memory read operations with different test values for the reference trim. The memory built-in self-test system also includes a trim feedback circuit to determine when the memory device fails to correctly sense the values of the stored data using the test values for the reference trim, and set the reference trim for the memory device based, at least in part, on the failures of the memory device to correctly sense the stored data.

Memory built-in self-test with automated reference trim feedback for memory sensing

A memory device can sense stored data during memory read operations using a reference trim, and a memory built-in self-test system can perform a multiple step process to set the reference trim for the memory device. The memory built-in self-test system can set a reference trim range that corresponds to a range of available reference trim values and then select one of the reference trim values in the reference trim range as the reference trim for the memory device. The memory built-in self-test system can set the reference trim range by prompting performance of the memory read operations using different positions of the reference trim range relative to read characteristics of the memory device and set a position for the reference trim range relative to the read characteristics of the memory device based on failures of the memory device to correctly sense the stored data during the memory read operations.

Memory built-in self-test with automated multiple step reference trimming

A reconfigurable scan network in a circuit is configured such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault. A test pattern having a length equal to a length of the second path is shifted into the reconfigurable scan network, and a part or a whole of the test pattern is then shifted out from the reconfigurable scan network. The part or the whole of the test pattern being shifted out is analyzed to determine whether the programmable component has the stuck-at fault.

Reconfigurable scan network defect diagnosis

Aspects of the invention relate to test access architecture for stacked memory and logic dies. A test access interface for a logic die that is stacked under a memory die is disclosed. The disclosed test access interface can control testing logic core, interconnections with the memory die and with another logic die. The controlling of testing interconnections with the memory die is through a memory boundary scan register controller in the test access interface.

Test access architecture for stacked memory and logic dies

Aspects of the invention relate to test access architecture for stacked dies. The disclosed test access interface for a die can function as a stand-alone test access interface, allowing both pre-bond testing and post-bond testing of the die. In a stack of dies, the test access interface of a die may be enabled/disabled by the test access interface of an adjacent die.

Test access architecture for multi-die circuits

Test access architecture for stacked dies

Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern. Further, the one or more fault dictionaries in one embodiment are generated by: (a) for a first defect candidate, storing one or more first indicators indicative of test patterns detecting the first defect candidate, and (b) for a second defect candidate, storing at least a second indicator indicative of the test patterns that detect the second defect candidate, the second indicator comprising a bit mask that indicates which of the test patterns detecting the first defect candidate also detect the second defect candidate.

Fault dictionaries for integrated circuit yield and quality analysis methods and systems

Methods, apparatus, and systems for computing and analyzing integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.

Determining and analyzing integrated circuit yield and quality

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Sherwood, OR, United States of America

Martin Keim