Micrel, Incorporated

Micrel Semiconductor

Martin J Alter

Shekar Mallikarjunaswamy

Helmuth R Litfin

James Copland Moyer

Paul McKay Moore

James B Compton

Robert W Rumsey

Clyde M Brown, Jr

Robert Stephen Wrathall

John Durbin Husher

Charles Vinn

Martin E Garnett

Carlos A Laber

Hiu Fung Ip

Lawrence R Sample

Chuck Vinn

Michael R Hsing

Richard Dolan

Marty E Garnett

Stephen McCormack

George Chu

The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on a p-type substrate, and an asymmetric conductive spacer which acts as its gate. The LDMOS transistor also includes a source and a drain region on either side of the asymmetric conductive spacer, and a channel region formed by ion-implantation on the asymmetric conductive spacer. The height of the asymmetric conductive spacer increases from the source region to the drain region. The channel region is essentially completely under the asymmetric conductive spacer and has smaller length than that of the channel region of the prior art LDMOS transistors. The LDMOS transistor of the present invention also includes a field oxide layer surrounding the active region of the transistor, and a thin dielectric layer isolating the asymmetric conductive spacer from the n-type epitaxial layer.

LDMOS transistor with asymmetric spacer as gate

A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing. Also disclosed is a method for integrating this vertical DMOS with CMOS, bipolar and BCD to provide an optimized small, efficient die using the buried power buss approach and these technologies.

System for vertical DMOS with slots

A Schottky or PN diode is formed where a first cathode portion is an N epitaxial layer that is relatively lightly doped. An N+ buried layer is formed beneath the cathode for conducting the cathode current to a cathode contact. A more highly doped N-well is formed, as a second cathode portion, in the epitaxial layer so that the complete cathode comprises the N-well surrounded by the more lightly doped first cathode portion. An anode covers the upper areas of the first and second cathode portions so both portions conduct current when the diode is forward biased. When the diode is reverse biased, the depletion region in the central N-well will be relatively shallow but substantially planar so will have a relatively high breakdown voltage. The weak link for breakdown voltage will be the curved edge of the deeper depletion region in the lightly doped first cathode portion under the outer edges of the anode. Therefore, the N-well lowers the on-resistance without lowering the breakdown voltage.

Diode having high breakdown voltage and low on-resistance

In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.

Seal ring for mixed circuitry semiconductor devices

In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over the surface of the FET, and the passivation layer is etched to expose almost the entire top surface of the bus strips. A copper seed layer is then formed over the surface of the wafer, and a mask is formed to expose only the seed layer over the bus strips. The seed layer over the bus strips is then copper or gold electroplated to deposit a very thick metal layer, which effectively merges with the underlaying metal layer, to reduce on-resistance. The plating metal does not need to be passivated due to its thickness and wide line/space. Other techniques may also be used for depositing a thick metal over the exposed bus strips.

Power FET with low on-resistance using merged metal layers

An NMOS transistor includes a semiconductor substrate of a first conductivity type, first and second well regions of a second conductivity type formed spaced apart in the substrate, a conductive gate formed over the region between the spaced apart first and second well regions where the region of the substrate between the spaced apart first and second well regions forms the channel region, dielectric spacers formed on the sidewalls of the conductive gate, first and second heavily doped source and drain regions of the second conductivity type formed in the semiconductor substrate and being self-aligned to the edges of the dielectric spacers. The first and second well regions extend from the respective heavily doped regions through an area under the spacers to the third well region. The first and second well regions bridge the source and drain regions to the channel region of the transistor formed by the third well.

Transistors fabricated using a reduced cost CMOS process

A low dropout (LDO) regulator device includes an LDO regulator integrated circuit housed in a 4-pin quad flat no-lead (QFN) package where the exposed die paddle is used as the ground terminal. The LDO regulator integrated circuit is formed on a semiconductor substrate. The 4-pin QFN package includes four perimeter lands connected to the input terminal, the output terminal, the enable terminal and the bypass terminal of the LDO regulator integrated circuit. The die paddle is to be electrically connected to a ground potential to allow the ground current of the LDO regulator integrated circuit to flow through the substrate and the die paddle of the 4-pin QFN package.

LDO regulator with ground connection through package bottom

A power transistor formed on a semiconductor substrate and including a lateral array of polysilicon lines separated by alternating source and drain regions includes one or more body contact diffusion regions formed in the source regions where each body contact diffusion region has a length that extends to the edges of the two adjacent polysilicon lines, and one or more body pickup contacts where each body pickup contact is formed over a respective body contact diffusion region. In one embodiment, the body contact diffusion regions are formed in a fabrication process using ion implantation of dopants of a first type through a body diffusion mask. Each body contact diffusion region defined by an exposed area in the body diffusion mask has a drawn area that overlaps the respective two adjacent polysilicon lines.

Power FET with embedded body pickup

Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described. Another exemplary embodiment illustrated the use of chip-scale processes for interconnecting discrete integrated circuits.

Integrating chip scale packaging metallization into integrated circuit die structures

An integrated circuit package includes a semiconductor chip having a passivation layer forming the top surface of the semiconductor chip and a metal pad formed on the passivation layer and a discrete electronic device having a first terminal formed on a first surface and a second terminal formed on a second surface opposite the first surface of the discrete electronic device where the first surface of the discrete electronic device is attached to the metal pad using a conductive adhesive structure. The semiconductor chip and the discrete electronic device are encapsulated in an encapsulation material. An electrical connection is formed between the metal pad and one of a bond pad of the semiconductor chip or a package post of the integrated circuit package. In one embodiment, the metal pad is an aluminum pad and a metal line connects the metal pad to a bond pad of the semiconductor chip.

Schottky diode device with aluminum pickup of backside cathode

A transistor is formed with a source ballast resistor that regulates channel current. In an LDMOS transistor embodiment, the source ballast resistance may be formed using a high sheet resistance diffusion self aligned to the polysilicon gate, and/or by extending a depletion implant from under the polysilicon gate toward the source region. The teachings herein may be used to form effective ballast resistors for source and/or drain regions, and may be used in many types of transistors, including lateral and vertical transistors operating in a depletion or an enhancement mode, and BJT devices.

Ballast resistors for transistor devices

Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described.

Growing community of inventors

Los Altos, CA, United States of America

Martin J Alter