Infineon Technologies Ag

Other

Siemens Aktiengesellschaft

Qimonda Ag

Martin Gutsche

Harald Seidl

Thomas Hecht

Franz Kreupl

Bernhard Sell

Cay-Uwe Pinnow

Stefan Jakschik

Satish D Athavale

Josef Willer

Albert Birner

Stephan Kudelka

Rainer Bruchhaus

Peter Moll

Hua Shen

Uwe Schröder

Alfred Kersch

Katherine Lynn Saenger

Thomas Happ

Thomas J Shaw

Yun-Yu Wang

David Edward Kotecki

Robert B Laibowitz

Gerhard Kunkel

Martin Popp

Bernd Goebel

Ralf Symanczyk

Matthias Ilg

Uwe Schroeder

Jenny Lian

Dirk Schumann

Alexander Gschwandtner

Annette Saenger

Jörn Lützen

Bruno Spuler

Annette Sänger

J&ouml;rn L&uuml;tzen

Wolfgang Bergner

Annette S&auml;nger

Uwe Paul Schr&ouml;der

Anja Morgenschweis

Shrinivas Govindarajan

Matthias Schmeide

Matthias F&ouml;rster

Matthias Leonhardt

Bernd G&ouml;bel

Werner Steinhögl

Werner Steinh&ouml;gl

Juergen Wittmann

The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

Vertical interconnect structure, memory device and associated production method

A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures. The first and second auxiliary layer structures are removed to uncover the sublithographic structures.

Process for producing sublithographic structures

Method for producing a dielectric material on a semiconductor device and semiconductor device Method for producing a dielectric material on semiconductor device with an atomic layer deposition procedure, whereby an aluminum oxide nitride or a silicon oxide nitride or an aluminum silicon oxide nitride layer is deposited comprising a rare earth metal-element. The invention describes a semiconductor device with a dielectric layer comprising aluminum oxide nitride or silicon oxide nitride or an aluminum silicon oxide nitride comprising a rare earth metal element.

Method for producing a dielectric material on a semiconductor device and semiconductor device

The present invention relates to a stacked capacitor array and a fabrication method for a stacked capacitor array having a multiplicity of stacked capacitors, an insulator keeping at least two adjacent stacked capacitors mutually spaced apart, so that no electrical contact can arise between them and the stacked capacitors are mechanically stabilized.

Stacked capacitor array and fabrication method for a stacked capacitor array

A memory cell includes a first electrode comprising a nanowire, a second electrode, and phase-change material between the first electrode and the second electrode.

Resistivity changing memory cell having nanowire electrode

The invention provides a method for fabricating a memory device having memory cells which are formed on a microstructured driving unit (), in which method a shaping layer () is provided and is patterned in such a manner that vertical trench structures () are formed perpendicular to the surface of the driving unit (). Deposition of a seed layer () on side walls () of the trench structures () allows a crystallization agent () which has filled the trench structures (), during crystallization, to have grain boundaries perpendicular to electrode surfaces that are to be formed. This provides memory cells based on vertical ferroelectric capacitors in a chain FeRAM structure.

Method for fabricating memory cells for a memory device

A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.

Ferroelectric memory arrangement

The present invention provides a fabrication method for a trench capacitor having an insulation collar () in a silicon substrate (), having the steps of: providing a trench () in the silicon substrate (); providing the insulation collar () in the upper trench region as far as the top side of the silicon substrate (); depositing a layer () made of a metal oxide in the trench (); carrying out a thermal treatment for selectively reducing the layer (), a region of the layer () that lies below the insulation collar () above the silicon substrate () being reduced and being converted into a first capacitor electrode layer () made of a corresponding metal silicide, and a region of the layer () that lies above the insulation collar () not being reduced; selectively removing the non-reduced region of the layer () that lies above the insulation collar (); providing a capacitor dielectric layer () in the trench () above the first capacitor electrode layer (); and providing a second capacitor electrode layer () in the trench () above the capacitor dielectric layer ().

Fabrication method for a trench capacitor having an insulation collar

In a method for producing a microelectronic electrode structure a first wiring plane is prepared, an insulating region on the first wiring plane is provided, a through-hole in the insulating region is formed, a ring electrode in the through-hole is formed, and a second wiring plane is formed on the insulating region. The ring electrode comprises a first side and a second side, the ring electrode is electrically connected on the first side to the first wiring plane, and the second wiring plane is electrically connected to the second side of the ring electrode.

Method of producing a microelectronic electrode structure, and microelectronic electrode structure

The present invention provides a fabrication method for a semiconductor structure having integrated capacitors and a corresponding semiconductor structure. The fabrication method has the following steps of: providing a semiconductor substrate (&#x2033;) having a front side (VS) and a rear side (RS); providing trenches () in the semiconductor substrate (&#x2033;) proceeding from the front side (VS) of the semiconductor substrate (&#x2033;); providing a respective inner capacitor electrode () in the trenches (); uncovering the inner capacitor electrodes () proceeding from the rear side (RS) of the semiconductor substrate (&#x2033;); providing a capacitor dielectric () on the uncovered inner capacitor electrodes (); and providing outer capacitor electrodes () on the capacitor dielectric () on the inner capacitor electrodes ().

Fabrication method for a semiconductor structure having integrated capacitors

The present invention provides a method for fabricating a capacitive element (), a substrate () being provided as a first electrode layer of the capacitive element (), the substrate () provided as an electrode layer is conditioned, a dielectric layer () is deposited on the conditioned substrate () and a second electrode layer () is applied on the layer stack produced, the layer stack being modified by a heat treatment in such a way that the dielectric layer () deposited on the conditioned substrate () forms a dielectric mixed layer () with a reaction layer () deposited on the dielectric layer (), which dielectric mixed layer has an increased dielectric constant (k) or an increased thermal stability.

Method of fabricating dielectric mixed layers and capacitive element and use thereof

A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is laterally removed adjacent the source/drain regions in order to form recesses, which are subsequently filled with a material that is appropriate for charge-trapping. The device structure and production method are appropriate for an integration scheme comprising local interconnects of memory cells, a CMOS logic periphery and means to compensate differences of the layer levels in the array and the periphery.

Charge-trapping memory device and method for production

Growing community of inventors

Dorfen, Germany

Martin Gutsche