Intel Corporation

Google Inc.

Sony Corporation

Sony Group Corporation

Martin D Giles

Stephen M Cea

Rafael Rios

Kelin J Kuhn

Annalisa Cappellani

Titash Rakshit

Jack T Kavalieros

Seiyon Kim

Willy Rachmady

Peter Chang

Tahir Ghani

Ravi Pillarisetty

Markus Kuhn

Mark Stettler

Cory E Weber

Roza Kotlyar

Nancy M Zelick

Aaron A Budrevich

Lucian Shifren

Borna Obradovic

Robert S Chau

Brian S Doyle

Matthew V Metz

Mark L Doczy

Suman Datta

Justin K Brask

Mark T Bohr

Sanaz Kabehie Gardner

David L Kencke

Peter G Tolchinsky

Jun He

Mohamad A Shaheen

Michael L McSwiney

Jose A Maiz

Thomas Hoffmann

Irwin Yablok

Zhiyong Ma

Everett X Wang

Been Y Jin

Guanghai Xu

Thomas Hoffman

Sanaz Kabehie

Philippe Matagne

Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.

Fins for metal oxide semiconductor device structures

Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Silicon and silicon germanium nanowire structures

Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

Nanowire structures having non-discrete source and drain regions

Embodiments of the present disclosure relate to non-planar semiconductor device structures having fins. In one embodiment, a semiconductor device includes a substrate, silicon fins positioned on the substrate, and a germanium layer that is epitaxially grown on an upper region of the silicon fins with the silicon fins and the germanium layer forming a body of the semiconductor device.

Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.

Semiconductor device having metallic source and drain regions

Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

Stress in trigate devices using complimentary gate fill materials

A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

Non-planar device having uniaxially strained semiconductor body and method of making same

Methods for forming fins for metal oxide semiconductor device structures

Growing community of inventors

Portland, OR, United States of America

Martin D Giles