Infineon Technologies Ag

Siemens Aktiengesellschaft

Other

International Business Machines Corporation

Lam Research Corporation

Semiconductor 300 Gmbh & Co. Kg

Sienens Aktiengesellschaft

Markus M Kirchhoff

Stephan Wege

Matthias Ilg

Son Van Nguyen

Maik Stegemann

Martin Schrems

Michael Jay Shapiro

William J Cote

Max Gerald Levy

Mirko Vogt

Ashima B Chakravarti

Zvonimir Gabric

Michael Rogalli

Donna Rizzone Cote

Oswald Spindler

Oliver Genz

Hans-Peter Sperlich

Momtchil Stavrev

Christoph Werner

Uwe Schilling

Barbara Schmidt

Manfred Hauf

Alexander Reb

Hans Glawischnig

Guenther Czech

Carsten Fuelber

Kevin A McKinley

Jochen Hanebeck

Stephan Machill

A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness comparable to that of diamond in at least one layer thickness section. During the production of this diamond-like layer thickness section, the parameters used in the deposition are set in such a manner that growth regions which are produced in a form other than diamond-like are removed again in situ by means of subsequent etching processes and that diamond-like regions which are formed are retained.

Photolithographic patterning process using a carbon hard mask layer of diamond-like hardness produced by a plasma-enhanced deposition process

A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.

Method for production of a semiconductor structure

Recesses between gate layer stacks are filled with a first electrically insulating material. Cavities or voids are opened up during the removal of a portion of the first insulating material. These voids are filled during the application of a conductive layer and can then lead to short circuits. Inventively, a layer for closing up voids is produced before the conductive material is applied, as a result of growing a second electrically insulating material onto the surface of the remaining first insulating material. This second insulating layer closes up voids that have formed in the first insulating material so that they can no longer lead to short circuits. In particular, voids that are difficult to gain access to and open out into side walls of contact holes can in this way be closed up in a simple manner.

Method for fabricating an integrated semiconductor circuit to prevent formation of voids

A method for filling depressions in a surface of a semiconductor structure, and a semiconductor structure filled in this way. On a semiconductor structure, in depressions on the surface, in particular below the first metal structure plane, a diffusion barrier layer is deposited, preferably with the aid of plasma-enhanced vapor phase deposition, during which the ions contained in the plasma are accelerated perpendicularly to the surface, resulting in non-conformal deposition of the diffusion barrier layer.

Method for filling depressions in a surface of a semiconductor structure, and a semiconductor structure filled in this way

A method for fabricating an insulator on a semiconductor substrate such that the insulator has a low dielectric constant. A first interconnect and a second interconnect are configured on a semiconductor substrate. A conductive silicon is formed between the first interconnect and the second interconnect. The conductive silicon is anodically etched in a hydrofluoric-acid-containing electrolyte to convert the conductive silicon into porous silicon. The porous silicon is subsequently oxidized to form porous silicon oxide. With a dielectric constant of between 1.1 and 4, the porous silicon oxide has a lower dielectric constant than customary silicon oxide with 4.

Method for forming an insulator having a low dielectric constant on a semiconductor substrate

A method in which a recess is formed in the surface of a semiconductor substrate and a material is grown on the inner wall of the recess, includes the steps of producing an electrically insulating layer on the surface of the substrate outside the recess, and selectively growing the material on the inner wall of the recess as a result of the substrate, as an electrode, being brought into contact with an electrolysis liquid and electrolysis being carried out, during which the insulating layer prevents the material from growing outside the recess. Before the electrolysis is carried out, a reserve material is epitaxially deposited on the inner wall of the recess and, during the electrolysis, the reserve material is converted into the material being grown by electrolysis.

Method for filling trenches in integrated semiconductor circuits

A method for forming a trench in a semiconductor substrate includes configuring a mask on the substrate. The mask has a window in which a substrate surface is uncovered. The substrate is electrochemically etched proceeding from the substrate surface. A porous substrate is formed in a trench-shaped region proceeding from the substrate surface. The trench is formed by removing the porous substrate from the trench-shaped region.

Method for forming a trench in a semiconductor substrate

A method of filling gaps on a semiconductor wafer with a dielectric material employs a plasma enhanced chemical vapor deposition (PECVD) process with a temperature in the range of 500 to 700&deg; C. As a result of the deposition process, gaps resulting from e.g. shallow trench isolation or premetal dielectric techniques are filled homogeneously without any voids. The deposition may be improved by applying two radio frequency signals with different frequencies.

Method of filling gaps on a semiconductor wafer

A process for fabricating a device including the step of forming a structure for facilitating the passivation of surface states is disclosed. The structure comprises an oxynitride layer formed as part of the device structure. The oxynitride facilitates the passivation of surface states when heated.

Semiconductor device structure with hydrogen-rich layer for facilitating passivation of surface states

A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.

Deposition of various base layers for selective layer growth in semiconductor production

The present invention relates to a dielectric filling for electrical wiring planes of an integrated circuit. The electrical wiring of the integrated circuit comprises a base body on which track and passivation planes can already be disposed; a conductive layer which is disposed on the base body and is patterned in such a manner that it exhibits a first conductor track, a second conductor track and a trench between the first conductor track and the second conductor track; at least one dielectric layer is disposed on the conductive layer and at least partially fills the trench, the preferred material of the dielectric layer being the polymer material polybenzoxazole.

Dielectric filling of electrical wiring planes

Improved gap fill of narrow spaces is achieved by using a doped silicate glass having a dopant concentration in a bottom portion thereof which is greater than an amount which causes surface crystal growth and in an upper portion thereof having a lower dopant concentration such that the overall dopant concentration of the doped silicate glass is below that which causes surface crystal growth.

Gapfill of semiconductor structure using doped silicate glasses

An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. It is a preferred method of the invention to perform the deposition at a temperature of about 750-850.degree. C. and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface. A F-BPSG glass and semiconductor wafers having a layer of fluorine doped BPSG thereon formed by the method and apparatus of the invention are also provided.

Low temperature reflow dielectric-fluorinated BPSG

A method in a plasma processing chamber for improving oxide-to-nitride selectivity while etching a borophosphosilicate glass (BPSG)-containing layer to create a self-aligned contact on a semiconductor substrate. The (BPSG)-containing layer is disposed on a SiN layer and into a via formed through the SiN layer. The method includes placing the substrate into the plasma processing chamber, and flowing an etchant source gas into the plasma processing chamber. The etchant source gas includes C.sub.4 F.sub.8 and an additive gas other than carbon monoxide (CO). The additive gas includes molecules having both oxygen atoms and carbon atoms in a 1:1 ratio. The method further includes exciting the etchant source gas with a radio frequency (RF) power source having a frequency of 13.56 MHz to strike a plasma from the etchant source gas, thereby etching at least partially through the BPSG-containing layer.

Growing community of inventors

Ottendorf-Olrilla, Germany

Markus M Kirchhoff