Globalfoundries Inc.

Advanced Micro Devices Corporation

Conversant Intellectual Property Management Incorporated

Markus Lenski

Stephan Kronholz

Anthony Mowry

Andy C Wei

Andreas Gehring

Ralf Richter

Vassilios Papageorgiou

Klaus Hempel

Frank Seliger

Jan Hoentschel

Thorsten E Kammler

Thomas Feudel

Robert Binder

Joachim Metzger

Ralf Otterbach

Fred N Hause

Sven Beyer

Casey Scott

Kerstin Ruttloff

Katja Huy

David G Farber

Thilo Scheiper

Rolf Stephan

Richard Carter

Ralf Van Bentum

Clemens Fitz

Stephan Kruegel

Joachim Patzer

Gunda Beernink

Dominic Thurmer

Vivien Schroeder

Ardechir Pakfar

Volker Jaschke

Guido Koerner

Peter Baars

Manfred Horstmann

Karsten Wieczorek

Peter Javorka

Roman Boschke

Hartmut Ruelke

Hans-Juergen Thees

Jens Heinrich

Elliot John Smith

Carsten Peters

Martin Trentzsch

Frank Wirbeleit

Martin Gerhardt

Gunter Grasshoff

Torsten Huisinga

Martin Mazur

Berthold Reimer

Patrick Press

Gerd Marxsen

Andreas Ott

Michael Raab

Kristin Schupke

Wolfgang Buchholtz

Frank Richter

Karla Romero

Joanna Wasyluk

Bastian Haussdoerfer

Loic Gaben

Sven Metzger

Ekkehard Pruefer

Roland Stejskal

Nadja Zakowsky

Jochen Poth

Sivakumar Kumarasamy

Marcus Wolf

Stephen Kronholz

Hartmut Rülke

In various aspects, the present disclosure relates to device structures and a method of forming such a device structure. In some illustrative embodiments herein, a device is provided, including a semiconductor substrate having a first trench formed therein, and a first trench isolation structure formed in the first trench. The first trench isolation structure includes first and second insulating liners formed adjacent inner surfaces of the first trench, wherein the first insulating liner is in direct contact with inner surfaces of the first trench and the second insulating liner is formed directly on the first insulating liner, and a first insulating filling material which at least partially fills the first trench. In some aspects, a thickness of the first insulating liner is greater than a thickness of the second insulating liner.

Front-end-of-line device structure and method of forming such a front-end-of-line device structure

A method includes providing a semiconductor structure including at least one first circuit element including a first semiconductor material and at least one second circuit element including a second semiconductor material. A dielectric layer having an intrinsic stress is formed that includes a first portion over the at least one first circuit element and a second portion over the at least one second circuit element. A first annealing process is performed, wherein an intrinsic stress is created at least in the first semiconductor material by stress memorization, and thereafter the first portion of the dielectric layer is removed. A layer of a metal is formed, and a second annealing process is performed, wherein the metal and the first semiconductor material react chemically to form a silicide. The second portion of the dielectric layer substantially prevents a chemical reaction between the second semiconductor material and the metal.

Method of forming a semiconductor structure including silicided and non-silicided circuit elements

Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers.

Methods for fabricating integrated circuits with robust gate electrode structure protection

In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.

High-K metal gate electrode structures formed by cap layer removal without sacrificial spacer

In advanced semiconductor devices, spacer elements may be formed on the basis of a multi-station deposition technique, wherein a certain degree of variability of the various sub-layers of the spacer materials, such as a different thickness, may be applied in order to enhance etch conditions during the subsequent anisotropic etch process. Consequently, spacer elements of improved shape may result in superior deposition conditions when using a stress-inducing dielectric material. Consequently, yield losses due to contact failures in densely packed device areas, such as static RAM areas, may be reduced.

Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device

A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less. A strain-inducing semiconductor alloy is embedded in the semiconductor region laterally adjacent to the bottom portion of the gate electrode structure, and drain and source regions are at least partially positioned in the strain-inducing semiconductor alloy.

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process.

Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material

By reducing a deposition rate and maintaining a low bias power in a plasma atmosphere, a spacer layer, for example a silicon nitride layer, may be deposited that exhibits tensile stress. The amount of tensile stress is controllable within a wide range, thereby providing the potential for forming sidewall spacer elements that modify the charge carrier mobility and thus the conductivity of the channel region of a field effect transistor.

Spacer for a gate electrode having tensile stress and a method of forming the same

In a stacked chip configuration, the 'inter chip' connection is established on the basis of functional molecules, thereby providing a fast and space-efficient communication between the different semiconductor chips.

Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules

When forming sophisticated semiconductor devices including complementary transistors having a reduced gate length, the individual transistor characteristics may be adjusted on the basis of individually provided semiconductor alloys, such as a silicon/germanium alloy for P-channel transistors and a silicon/phosphorous semiconductor alloy for N-channel transistors. To this end, a superior hard mask patterning regime may be applied in order to provide compatibility with sophisticated replacement gate approaches, while avoiding undue process non-uniformities, in particular with respect to the removal of a dielectric cap layer.

Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas

The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130&#xb0; C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni'/Pt layer at a temperature of 130&#xb0; C.

NiSi rework procedure to remove platinum residuals

Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.

One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted HF acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.

Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions

A silicon dioxide material may be provided in sophisticated semiconductor devices in the form of a double liner including an undoped silicon dioxide material in combination with a high density plasma silicon dioxide, thereby providing reduced dependency on pattern density. In some illustrative embodiments, the silicon dioxide double liner may be used as a spacer material and as a hard mask material in process strategies for incorporating a strain-inducing semiconductor material.

Oxide deposition by using a double liner approach for reducing pattern density dependence in sophisticated semiconductor devices

One method disclosed includes forming a gate structure of a transistor above a surface of a semiconducting substrate, forming a sidewall spacer proximate the gate structure, forming a sacrificial layer of material above the protective cap layer, sidewall spacer and substrate, forming an OPL layer above the sacrificial layer, reducing a thickness of the OPL layer such that, after the reduction, an upper surface of the OPL layer is positioned at a level that is below a level of an upper surface of the protective cap layer, performing a first etching process to remove the sacrificial layer from above the protective cap layer to expose the protective cap layer for further processing, performing a second etching process to remove the protective cap layer and performing at least one process operation to remove at least one of the OPL layer or the sacrificial layer from above the surface of the substrate.

Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regions

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Dresden, Germany

Markus Lenski