International Business Machines Corporation

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Marvell International Limited

Globalfoundries U.S. 2 LLC

Marvell Government Solutions, LLC.

Mark William Kuemerle

Susan K Lichtensteiger

Jeanne P Bickford

Eric A Foreman

Wolfgang Sauter

Igor Arsovski

Eric W Tremble

Clarence Rosser Ogilvie

David W Milton

Jack Robert Smith

Christopher Douglas Hanudel

Malede Wondmagegne Berhanu

Nicholas A Polomoff

David James Hathaway

David Brian Stone

Jeffrey G Hemmett

Douglas Willard Stout

Eric D Hunt-Schroeder

Luke G England

Qing Li

Edmund D Blackshear

Ivan L Wemple

Jeanne P S Bickford

Seungman Choi

Jeanne H Raymond

Eric S Parent

Jawahar P Nayak

Daniel P Greenberg

Paul S Zuchowski

Aatreya Chakravarti

Samer Michael Akiki

Christoph Sauter

A system for designing placement locations for Input/Output (I/O) blocks in an electronic device is disclosed. The system includes an interface and a processor. The interface is configured to receive a requirement that specifies at least multiple I/O blocks to be laid-out along a periphery of an electronic device that implements a network communication device. The processor is configured to generate a plurality of candidate layouts for the electronic device, the candidate layouts differing from one another at least in an arrangement of the specified I/O blocks along the periphery, to estimate respective costs associated with at least some of the candidate layouts, and to present at least some of the candidate layouts and the respective estimated costs to a user.

Quick floorplanning tool

An electronic network device includes: (i) an integrated circuit (IC) die configured to exchange signals between the electronic network device and one or more other devices that are remote from the electronic network device, (ii) a plurality of transceiver dies, separate from the IC die, the plurality of transceiver dies being disposed along at least a first axis extending at an acute angle from an edge of the IC die and intersecting the edge at a first point, the transceiver dies being configured to exchange the signals between the IC die and the other devices, and (iii) electrical connections configured to connect between the IC die and at least one of the transceiver dies for exchanging at least some of the signals between the IC die and the transceiver dies.

Lateral escape using triangular structure of transceivers

The present disclosure relates to semiconductor structures and, more particularly, to partitioned substrates with interconnect bridge structures and methods of manufacture. The structure includes: a plurality of substrates; at least one chip bonded and electrically connected to each of the plurality of substrates; and an interconnect bridge that physically connects the plurality of substrates and electrically connects each of the plurality of chips bonded to each of the plurality of substrates.

Partitioned substrates with interconnect bridge

A barrier or 'crackstop' that is configured to conduct electrical signals. These configurations may form a wall around integrated, active circuitry of a semiconductor die. This wall may include a conductor that follows a three-dimensional pathway from one side to the other side of the wall. This pathway may have sections that overlap, or double-back, so that portions of the conductor overlap along their individual length. These sections prevent crack propagation internal to the wall.

Hermetic barrier for semiconductor device

Disclosed is a multi-chip module (MCM) with redundant chip-to-chip communication connection(s) to minimize the need to discard a chip-mounting layer due to defective signal traces. The MCM includes at least first and second chips mounted on the chip-mounting layer. The chip-mounting layer includes signal traces that are electrically connected between first and second links on the first and second chips, respectively, to form communication connections including at least one redundant communication connection. Instead of being directly connected to the chip-to-chip communication connections, first and second interfaces on the first and second chips are connected via first and second multiplexors, respectively, to selected ones of multiple chip-to-chip communication connections. By employing the multiplexors and the redundant chip-to-chip communication connection(s), chip-to-chip communication connection(s) with defective signal trace(s) can be bypassed. Specifically, during MCM assembly, the multiplexors are programmed to avoid using chip-to-chip communication connections with defective signal traces.

Multi-chip module (MCM) with chip-to-chip connection redundancy and method

An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

Interconnected integrated circuit (IC) chip structure and packaging and method of forming same

The present disclosure relates to semiconductor structures and, more particularly, to an interconnect structure to connect between different package configurations and methods of manufacture. The structure includes an interconnect comprising a plurality of conductive levels and columns configured into a grid pattern within an insulator material, the plurality of conductive levels and columns aligned to connect to different package configurations; and a control circuit that provides a signal to the interconnect to connect to a combination of the different package configurations.

Interconnect structure

The present disclosure relates to interface structures and, more particularly, to integrated interface structures with both parallel and serial interfaces and methods of manufacture. The integrated interface structure includes: a substrate; a plurality of serial interface connections integrated on the substrate; and a plurality of parallel interface connections on the integrated substrate and within spaces between sets of the plurality of serial interface connections.

Integrated interface structure

The present disclosure relates to memory structures and, more particularly, to double bandwidth algorithmic memory array structures and methods of use. The memory array includes: a plurality of memory banks each of which includes addressable storage units; a redundant array of independent disks (RAID) bank which stores parity bits corresponding to data written into any of the plurality of memory banks at a same address; and a plurality of XOR gates in which data written into any of the plurality of memory banks is cascaded therethrough to refresh the parity bits in the RAID bank.

Double bandwidth algorithmic memory array

Systems and methods for optimizing timing/power risk SVB using a customer-supplied, non-linear voltage slope. Chips are manufactured according to an integrated circuit design. The minimum operating voltage and hardware variations for each device in the design is determined and a process distribution for the chips is divided into process windows. Vmax and Vmin to support system frequency are determined for each process window. Vmin vs. process-bin mean and sigma sensitivity is calculated using information about specific devices. The voltage for each process window that generates Vmin for specific devices is identified. Power at the slow end and fast end of each process window is evaluated using the voltage to support system frequency. Pmax is determined. Vmax for each process window that generates Pmax is determined. A voltage is identified between Vmin and Vmax that maximizes the timing margin for system frequency while minimizing risk for Pmax. The chips are sorted into different process windows, based on the voltage identified.

Timing/power risk optimized selective voltage binning using non-linear voltage slope

Design methods and systems disclosed use a process window-aware timing analysis of an integrated circuit (IC) chip design for improved accuracy. Specifically, a process distribution for the design is defined and divided into process windows. Timing parameter adjustment factors are assigned to the process windows. A timing analysis is performed in order to acquire an initial solution for a timing parameter (e.g., delay, slack or slew). For each specific process window, this initial solution is adjusted by the predetermined timing parameter adjustment factor assigned to that specific process window. The adjusted solutions for the different process windows account for process window-to-process window variations in the widths of distribution of a process parameter (e.g., leakage power) and can be used to predict whether IC chips manufactured according the IC chip design will meet established timing requirements (e.g., required arrival times (RATs)) regardless of where they fall within the process distribution.

Integrated circuit chip design methods and systems using process window-aware timing analysis

Disclosed are a system and method that control integrated circuit chip temperature using frequency scaling based on predetermined temperature-frequency settings. During integrated circuit chip operation, a controller causes a variable clock signal generator to adjust the frequency of a clock signal that coordinates operations of an integrated circuit chip based on the temperature of the integrated circuit chip and on predetermined temperature-frequency settings. The temperature-frequency settings are predetermined in order to ensure that the frequency of the clock signal, as adjusted, remains sufficiently high to meet a chip performance specification, but sufficiently low to prevent the temperature from rising above a predetermined maximum temperature in order to limit power consumption. Also disclosed is a method of generating such temperature-frequency settings during timing analysis.

Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling

A computing device for a generating composite view for an intellectual property (IP) core may obtain constraints for multiple application specific integrated circuits (ASIC) designs in which the IP core is used; and determine composite constraints for the IP core based on the constraints for the multiple ASIC designs. The composite constraints may be within all constraints for the multiple ASIC designs. A freedom of change to update the particular IP core may be identified based on the composite constraints.

Composite views for IP blocks in ASIC designs

Various embodiments provide systems, computer program products and computer implemented methods. In some embodiments, the system includes a computer-implemented method of binning at least one integrated circuit chip, the method including determining a baseline operational voltage for the at least one integrated circuit chip, determining a total operational power threshold for the at least one integrated circuit chip, determining an initial performance characteristic for a first component of the at least one integrated circuit chip, operating the first component at a driving voltage higher than the baseline voltage to raise the initial performance characteristic of the first component to a raised performance characteristic while ensuring that operational power does not exceed the operational power threshold and assigning the at least one integrated circuit chip to a performance bin based on the raised performance characteristic.

Reverse performance binning

Disclosed is a system that periodically increases the supply voltage applied to a power rail of an integrated circuit chip that is incorporated into a product, thereby compensating for age-dependent changes in a performance parameter sensitivity (e.g., in a delay sensitivity). In this system, the chip comprises at least a memory, an age monitor, a voltage selector and a power rail. The memory stores an age/voltage table. The age monitor automatically measures the age of the chip. Based on the age and using the age/voltage table, the voltage selector selects a specific supply voltage and outputs a voltage selection signal to an adjustable voltage regulator, which can apply (e.g., automatically or on-demand) that specific supply voltage to the power rail. Also disclosed is a method for regulating the power supplied to an integrated circuit chip, which is incorporated into a product, and a method for generating an age/voltage table.

Growing community of inventors

Essex Junction, VT, United States of America

Mark William Kuemerle