Synopsys, Inc.

Mark William Bales

Jeffrey Jude Loescher

David L Peart

Paul M Furnanz

John Ralph Chase

In general, embodiments of the present invention provide systems, methods and computer readable media for generating a tiling for a physical placement of a plurality of circuits. The method includes generating a tiling including a plurality of tiles, where each tile identifies a tile geometric area, and a list of one or more of the circuits to be placed in the tile geometric area. The tiling is based on a description of one or more user constraints, where each user constraint identifies a constraint geometric area, and a characteristic of circuits to be placed in the constraint geometric area.

IC physical design using a tiling engine

Systems and methods allow an IC design process to continue in the face of errors while those errors are being investigated and fixed in the actual design data. Potential mismatches can be categorized and a user can choose which action (if any) to take when a specific mismatch is discovered. A set of potential mismatches and their action settings can be aggregated into a higher level setting that the end user of the system can choose during different stages of a design project. A record of the mismatches that have been encountered, the design elements that are involved in each mismatch, and what action where taken to repair the mismatch is kept and maintained.

Method for organizing, controlling, and reporting on design mismatch information in IC physical design data

A method of establishing regions for placing cells of an integrated circuit (IC) includes, in part, assigning a precedence value to each of a multitude of constraint regions of the IC, and forming a multitude regions each associated with one of the constraint regions. The region associated with each constraint region is formed in accordance with the precedence value of its associated constraint region and the precedence values associated with any other constraint regions overlapping the first constraint region. Each region in a subset of the constraint regions is further defined in accordance with the region's transparency/opacity attribute.

Management of placement constraint regions in an electronic design automation (EDA) system

In Integrated Circuit (IC) Physical Design, the shapes and other geometric objects that are used to represent the mask data have physical coordinates expressed in a Cartesian plane. When the designs are hierarchical, each level of physical hierarchy has its own coordinate system. When viewed from the top level of a hierarchical design, lower-level shapes must be transformed in order to understand their location from the point of view of the top block. Users and algorithms that manipulate physical data across these hierarchy boundaries must go through the tedious task of transforming data, sometimes multiple times, as it is being changed.

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Livermore, CA, United States of America

Mark William Bales