Intel Corporation

Mark S Hlad

Mihir K Roy

Mathew J Manusharow

Tao Wu

Ravi Kiran Nalla

Harold Ryan Chase

Aleksandar Aleksov

Islam A Salama

Kyu Oh Lee

Edward Rudolph Prack

Yueli Liu

Tony Dambrauskas

Danish Faruqui

Sanka Ganesan

Charan K Gurumurthy

Amanda E Schuckman

Christine Tsau

Srinivas V Pietambaram

Kristof Darmawikarta

Sri Ranga Sai Boyapati

Sheng C Li

Qinglei Zhang

Sashi S Kandanur

Charavana K Gurumurthy

Chandrashekhar Ramaswamy

Chandrashekar Ramaswamy

A method that includes electroplating both sides of a core and the through hole of a core with a conductive material to cover both sides of the core with the conductive material and to form a conductive bridge in the through hole, wherein the core has a thickness greater than 200 microns; etching the conductive material that covers both sides of the core to reduce the thickness of the conductive material to about 1 micron; applying a film resist to the core; exposing and developing the resist film to form patterns on the conductive material on both sides of the core; and electroplating additional conductive material on the (i) conductive material on both sides of the core (ii) conductive material within the through hole; and (iii) conductive bridge to fill the through hole with conductive material without any voids and to form conductive patterns on both sides of the core.

Electronic assembly that includes void free holes

Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.

Substrate conductor structure and method

Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.

Organic thin film passivation of metal interconnections

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Device packaging with substrates having embedded lines and metal defined pads

A bumpless build-up layer (BBUL) integrated circuit package and method of manufacturing are presented. In some embodiments, the package-on-package (PoP) pads of the BBUL integrated circuit package has a surface finish that can be palladium, nickel-palladium, nickel-gold, nickel-palladium-gold, or palladium-nickel-palladium-gold. In some embodiments, the PoP pad surface finish can be formed using either an electroless or electrolytic process.

Enabling package-on-package (PoP) pad surface finishes on bumpless build-up layer (BBUL) package

Non-cylindrical conducting shapes are described in the context of multilayer laminated substrate cores. In one example a package substrate core includes a plurality of dielectric layers pressed together to form a multilayer core, a conductive bottom pattern on a bottom surface of the multilayer core, and a conductive top pattern on a top surface of the multilayer core. At least one elongated via extends through each layer of the multilayer core, each elongated via containing a conductor and each connected to a conductor of a via in an adjacent layer to electrically connect the top pattern and the bottom pattern through the conductors of the elongated vias.

Non-cylindrical conducting shapes in multilayer laminated substrate cores

Embodiments of the present disclosure are directed towards techniques and configurations for providing void-free filled interconnect structures in a dielectric layer of a package assembly. In one embodiment, the method for providing a void-free filled interconnect structure may include forming a through hole through a layer of a package substrate, and depositing a conductive material to fill the through hole. Depositing the conductive material may be performed while gradually increasing a current density of the conductive material and correspondingly changing a flow rate of the conductive material. Other embodiments may be described and/or claimed.

Providing a void-free filled interconnect structure in a layer of package substrate

A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.

Bumpless build-up layer and laminated core hybrid structures and methods of assembling same

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Gainsville, FL, United States of America

Mark S Hlad