Dow Corning Corporation

Dow Silicones Corporation

Hemlock Semiconductor Operations LLC

Sk Siltron Css, LLC

Ddp Specialty Electronic Materials US 9, LLC

Mark Jon Loboda

Keith W Michael

Christopher Parfeniuk

Darren Hansen

Byung Keun Hwang

Gilyong Y Chung

Victor Torres

Loren A Haluska

Kevin J Moeggenborg

Robert Charles Camilletti

Steven A Snow

William Kenneth Weidner

David S Ballance

Ludmil M Zambov

Jeffrey Alan Seifferly

Clinton Whiteley

Stephan Mueller

Roman Drachev

Edward Sanchez

Jeffrey Quast

Ian Manning

Dimitris Katsoulis

Udo C Pernisz

Andrew Jules Steckl

James C Mundell

Chong Yuan

Glenn Allen Cerny

Marie N Eckstein

Seung Ho Park

Ji-Ping Li

Diana Kay Deese

Brian S Cichowski

James J Mueller

Christopher S Robinson

Vasgen A Shamamian

Elizabeth McQuiston

Luisel Rodriguez

Jie Zhang

Liberty B Shelton

Steven Snow

A method of removing surface carbon contamination from polycrystalline silicon comprises providing a polycrystalline silicon feed stream having surface carbon contamination, subjecting the polycrystalline silicon to a high velocity fluid selected from gas, gas/liquid mixtures, gas/solid mixtures and gas/solid/liquid mixtures to form a product stream comprising polycrystalline silicon having surface carbon in an amount of less than 200 parts per billion by weight based on weight of the polycrystalline silicon product and/or a reduction in surface carbon contamination of at least 20%. A system for conducting the method comprises an enclosure, a conveyer for moving a polycrystalline silicon feed stream through the enclosure, at least one stream of a high velocity fluid passing through outlets in the enclosure and directed at the feed stream, an ionizing source in the enclosure or integrated with the at least one stream of high velocity fluid, and an exhaust system for the enclosure.

Method and apparatus for removal of surface carbon from polysilicon

An apparatus for physical vapor transport growth of semiconductor crystals having a cylindrical vacuum enclosure defining an axis of symmetry; a reaction-cell support for supporting a reaction cell inside the vacuum enclosure; a cylindrical reaction cell made of material that is transparent to RF energy and having a height Hcell defined along the axis of symmetry; an RF coil provided around exterior of the vacuum enclosure and axially centered about the axis of symmetry, wherein the RF coil is configured to generate a uniform RF field along at least the height Hcell; and, an insulation configured for generating thermal gradient inside the reaction cell along the axis of symmetry. The ratio of height of the RF induction coil, measured along the axis of symmetry, to the height Hcell may range from 2.5 to 4.0 or from 2.8 to 4.0.

Furnace for seeded sublimation of wide band gap crystals

A method of forming an SiC crystal including placing in an insulated graphite container a seed crystal of SiC, and supporting the seed crystal on a shelf, wherein cushion rings contact the seed crystal on a periphery of top and bottom surfaces of the seed crystal, and where the graphite container does not contact a side surface of the seed crystal; placing a source of Si and C atoms in the insulated graphite container, where the source of Si and C atoms is for transport to the seed crystal to grow the SiC crystal; placing the graphite container in a furnace; heating the furnace; evacuating the furnace; filling the furnace with an inert gas; and maintaining the furnace to support crystal growth to thereby form the SiC crystal.

Graphite crucible for sublimation growth of SiC crystal

A method of forming an SiC crystal, the method including: placing a SiC seed in a growth vessel, heating the growth vessel, and evacuating the growth vessel, wherein the seed is levitated as a result of a temperature and pressure gradient, and gas flows from a growth face of the seed, around the edge of the seed, and into a volume behind the seed, which is pumped by a vacuum system.

Reaction cell for growing SiC crystal with low dislocation density

A method for producing silicon carbide substrates fit for epitaxial growth in a standard epitaxial chamber normally used for silicon wafers processing. Strict limitations are placed on any substrate that is to be processed in a chamber normally used for silicon substrates, so as to avoid contamination of the silicon wafers. To take full advantage of standard silicon processing equipment, the SiC substrates are of diameter of at least 150 mm. For proper growth of the SiC boule, the growth crucible is made to have interior volume that is six to twelve times the final growth volume of the boule. Also, the interior volume of the crucible is made to have height to width ratio of 0.8 to 4.0. Strict limits are placed on contamination, particles, and defects in each substrate.

Method for manufacturing SiC wafer fit for integration with power device manufacturing technology

Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a support shelf which permits thermal expansion

Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a supporting shelf which permits thermal expansion

4H SIC epiwafers with thickness of 50-100 &#x3bc;m are grown on 4&#xb0; off-axis substrates. Surface morphological defect density in the range of 2-6 cmis obtained from inspection of the epiwafers. Consistent carrier lifetime in the range of 2-3 &#x3bc;s has been obtained on these epiwafers. Very low BPD density has been confirmed in the epiwafers with BPD density down to below 10 cm. Epitaxial wafers with thickness of 50-100 &#x3bc;m have been used to fabricate diodes. High voltage testing has demonstrated blocking voltages near the theoretical values for 4H-SiC. Blocking voltage as high as 8 kV has been achieved in devices fabricated on 50 &#x3bc;m thick epitaxial films, and blocking voltage as high as 10 kV has been obtained in devices fabricated on 80 &#x3bc;m thick films. Failure analysis confirmed triangle defects, which form from surface damage or particles present during epitaxy, are killer defects and cause the device to fail in reverse bias operation. In addition, the leakage current at the high blocking voltages of the JBS diodes showed no correlation with the screw dislocation density. It is also observed that the main source of basal plane dislocations in the epilayer originates in the crystal growth process.

High voltage power semiconductor device on SiC

This invention relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a chlorosilane gas, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000&#xb0; C. but less than 2000&#xb0; C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. This invention also relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a non-chlorinated silicon-containing gas, hydrogen chloride, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000&#xb0; C. but less than 2000&#xb0; C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr.

Method of manufacturing substrates having improved carrier lifetimes

Heteroelement siloxane polymers are described. The heteroelement siloxane polymers can have linear structure, cyclic structure, branched structure, and three-dimensional network structure and combinations thereof. The heterosiloxane polymers can be cured using curing chemistry derived from thermoset organosilicon polymers, and gels, coatings, plaques, parts and other useful articles can be prepared.

Heteroelement siloxane compounds and polymers

Methods for manufacturing silicon carbide wafers having superior specifications for bow, warp, total thickness variation (TTV), local thickness variation (LTV), and site front side least squares focal plane range (SFQR). The resulting SiC wafer has a mirror-like surface that is fit for epitaxial deposition of SiC. The specifications for bow, warp, total thickness variation (TTV), local thickness variation (LTV), and site front side least squares focal plane range (SFQR) of the wafer are preserved following the addition of the epitaxy layer.

Flat SiC semiconductor substrate

A method of forming an SiC crystal including placing a seed crystal of SiC in an insulated graphite container; placing a source of Si and C atoms in the insulated graphite container, where the source of Si and C atoms is for transport to the seed crystal to grow the SiC crystal; placing the container into the furnace; heating a furnace to a temperature from about 2,000&#xb0; C. to about 2,500&#xb0; C.; evacuating the furnace to a pressure from about 0.1 Torr and about 100 Torr; filling the furnace with an inert gas; and introducing dopant gas into the furnace with a controlled flow so as to form a plurality of stratified layers wherein each layer has dopant concentration different from a layer directly below and a layer directly above it. A 4H-SiC crystal made by the method. A 4H-SiC substrate cut from the SiC crystal made from the method.

Method to reduce dislocations in SiC crystal growth

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Midland, MI, United States of America

Mark Jon Loboda