Advanced Micro Devices Corporation

Tokyo Electron Limited

Other

Infineon Technologies Ag

Advanced Miero Devices

Mark I Gardner

H Jim Fulford

Derick J Wristers

Daniel Kadosh

Mark C Gilmer

Frederick N Hause

Fred N Hause

Charles E May

Robert Louis Dawson

Mark W Michael

Bradley T Moore

Michael P Duane

Thomas E Spikes, Jr

Jon D Cheek

Partha Mukhopadhyay

Robert Paiz

Anton J deVillers

Kuang-Yeh Chang

Thien T Nguyen

Sey-Ping Sun

Dim-Lee Kwong

John J Bush

Lars W Liebmann

Daniel Chanemougame

Jeffrey Smith

Daniel J Fulford

Derrick J Wristers

Anthony R Schepis

Anthony John Toprac

Yowjuang William Liu

Robert Daniel Clark

Anton J Devilliers

Jack C Lee

Kandabara N Tapily

Hong-Jyh Li

Shengnian Davis Song

Minh Van Ngo

Michael J Allen

Subhadeep Kal

David E Brown

John Lee Nistler

David C Conklin

Andrew Weloth

Brad T Moore

Said N Ghneim

Jay J Seaton

Ronald Jacobs

Thomas E Spikes

Robert W Anderson

Sey Ping Sun

Steven C Hall

John Randolph Fisher

Daniel Kadoch

K Y Chang

Dayton S Whites

Thomas, Jr Spikes

Dayton E Whites

Jon C Cheek

H Jim Eulford, Jr

James Elliott Walters

A method of processing a substrate, including forming a photomask based on a layout of a first surface of a wafer including at least one opaque region and at least one transparent region and the first surface of the wafer being coated with a photosensitive resist; providing the photomask at a first photomask location between the first surface of the wafer and a source of radiation at a predetermined wavelength, the at least one opaque region of the photomask covering a first region of the first surface of the wafer and the at least one transparent region of the photomask exposing a second region of the first surface of the wafer; and exposing the first surface of wafer to a first pattern of radiation, the first pattern of radiation including the second region of the wafer exposed by the at least one transparent region of the photomask.

Method for selective exposure of wafer to corrective irradiation at a per-die level

Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with the dielectric structure. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.

3D isolation of a segmentated 3D nanosheet channel region

One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a source contact, a drain contact, a 2D material forming a channel between the source and drain contacts and surrounding a carrier nanosheet forming a first p-n junction with the source contact and a second p-n junction with the drain contact, and a gate structure comprising a gate dielectric and a gate contact contacting at least a portion of the channel between the first p-n junction and the second p-n junction. The source and drain contacts can comprise a doped semiconductor material and a channel having a first curved profile extending along the source contact and a second curved profile extending along the drain contact.

3D advanced transistor architecture integrated with source/drain spider design

A semiconductor structure includes semiconductor layers stacked vertically over a substrate. The structure includes a gate structure interleaved with the semiconductor layers, where the gate structure wraps around a first end portion of each semiconductor layer. The structure includes dielectric layers stacked vertically over the substrate and interleaved with the semiconductor layers, where a first end portion of each dielectric layer is aligned with a second end portion of each semiconductor layer, which is laterally opposite to the first end portion of each semiconductor layer. The structure includes a metal contact extending vertically to contact the second end portion of each semiconductor layer.

Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a semiconductor device includes a first transistor comprising a first channel region. The first channel region includes one or more first nanostructures formed of a semiconductor material. The semiconductor device includes a second transistor disposed vertically with respect to the first transistor and comprising a second channel region. The second channel region includes one or more second nanostructures formed of a conductive oxide material.

3D hybrid memory using horizontally oriented conductive dielectric channel regions

Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another, wherein different materials are simultaneously epitaxial-grown for the first semiconductor channels and the second semiconductor channels, can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with the dielectric structure. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.

High performance 3D compact transistor architecture

A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. Each DRAM cell unit includes a respective transistor, a respective capacitor and a respective bridge structure. Each bridge structure is configured to electrically couple the respective transistor to the respective capacitor. Each capacitor is elongated in a horizontal direction parallel to the working surface of the substrate.

3D horizontal DRAM with in-situ bridge

Aspects of the present disclosure provide a semiconductor structure, which can include a lower transistor including a lower channel that is elongated horizontally and includes a lower doped first-type semiconductor layer of a lower doped semiconductor layer, an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally and includes an upper doped first-type semiconductor layer of an upper doped semiconductor layer, a lower capacitor electrically connected to and horizontally elongated from the lower transistor and including a first lower plate that includes a lower doped second-type semiconductor layer of the lower doped semiconductor layer, and an upper capacitor vertically stacked over the lower capacitor and electrically connected to and horizontally elongated from the upper transistor and including a first upper plate that includes an upper doped second-type semiconductor layer of the upper doped semiconductor layer.

Three-dimensional plurality of N horizontal memory cells with enhanced high performance circuit density

Aspects of the present disclosure provide a method for optimizing wafer shape. For example, the method can include receiving a wafer having a working surface for one or more devices to be fabricated thereon and a backside surface opposite to the working surface, measuring the wafer to identify bow measurement of the wafer, and forming a stress-modification film on the backside surface of the wafer. The stress-modification film can be reactive to heat such that applied heat modifies an internal stress of the stress-modification film. The method can also include applying a pattern of heat onto the stress-modification film to modify the internal stress of the stress-modification film, the pattern of heat corresponding to the bow measurement.

In-situ lithography pattern enhancement with localized stress treatment tuning using heat zones

A semiconductor device may include a transistor structure. The transistor structure may include a metal structure extending along a vertical direction; a gate dielectric layer around the metal structure; a channel layer around the gate dielectric layer; a first metal electrode disposed below the metal structure and in electrical contact with a first end of the channel layer; a second metal electrode disposed above the metal structure and in electrical contact with a second end of the channel layer; and a third metal electrode disposed above and in electrical contact with the metal structure.

Vertical transistors and methods for forming the same

A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first channel structure positioned over a substrate, first source/drain (S/D) regions positioned on ends of the first channel structure, and a first gate structure disposed all around the first channel structure. The second transistor includes a second channel structure positioned over the first channel structure, second S/D regions positioned on ends of the second channel structure, and a second gate structure disposed all around the second channel structure. The second channel structure has a smaller dimension than the first channel structure in a horizontal direction substantially parallel to a working surface of the substrate.

Compact 3D design and connections with optimum 3D transistor stacking

Systems and methods are provided herein for determining the planarity of a semiconductor wafer. The systems and methods described herein utilize a capacitive measurement tool to detect and characterize the bow of a semiconductor wafer. The capacitive measurement tool disclosed herein utilizes a non-contact, capacitive sensor unit to measure wafer bow. Unlike conventional capacitive sensing techniques used to measure wafer bow, the capacitive sensor unit disclosed herein uses a plurality of electrodes for simultaneously obtaining a plurality of capacitance measurements from the wafer at various locations on the wafer surface. By including a plurality of electrodes within the capacitive sensor unit, the techniques described herein increase the amount of data collected across the wafer surface at any given time to improve the throughput and measurement accuracy of the capacitive measurement tool.

Contactless capacitive measurement tool with improved throughput and accuracy

A semiconductor device includes a memory cell unit positioned over a substrate. The memory cell unit includes a transistor and a capacitor. The capacitor includes an inner conductor, a capacitor dielectric all around the inner conductor, an outer conductor all around the capacitor dielectric, and dielectric support structures below the inner conductor. The capacitor is elongated in a length direction parallel to a working surface of the substrate, and the dielectric support structures are spaced along the length direction. The transistor includes a channel structure, a gate structure all around the channel structure, and source/drain (S/D) regions on opposing ends of the channel structure.

3D horizontal memory cell with sequential 3D vertical stacking

Aspects of the present disclosure provide a bonding device for bonding two wafers. For example, the bonding device can include a first bonding chuck and a second bonding chuck. The first bonding chuck can have a first bonding head for a first wafer to be mounted thereon. The second bonding chuck can have a plurality of second bonding heads for a second wafer to be mounted thereon. The second bonding heads can be controlled individually to apply local pressures onto the second wafer to move the second wafer toward the first wafer to bond the second wafer to the first wafer, the local pressures corresponding to bow measurement of the first wafer and the second wafer.

3D multiple location compressing bonded arm for advanced integration

One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a first carrier nanosheet at least partially surrounded by a first 2D material and a second carrier nanosheet at least partially surrounded by a second 2D material. The transistor can include a first source/drain structure in electrical contact with a first end of the first 2D material and a first end of the second 2D material. The transistor can include a second source/drain structure in electrical contact with a second end of the first 2D material and a second end of the second 2D material. The transistor can include a gate structure at least partially surrounding the first 2D material and the second 2D material.

2D material to integrate 3D horizontal nanosheets using a carrier nanosheet

Growing community of inventors

Cedar Creek, TX, United States of America

Mark I Gardner