Sandisk 3d LLC

Crossbar, Inc.

Intermolecular, Inc.

Sandisk Corporation

Matrix Semiconductor, Inc.

Gtat Corporation

Twin Creeks Technologies, Inc.

Twin Creek Technologies, Inc.

Mark Harold Clark

April Dawn Schricker

S Brad Herner

Steven Patrick Maxwell

Natividad Vasquez

Brad Herner

Prashant B Phatak

Tanmay Kumar

Harry Yue Gee

Ashish Bodke

Deepak Chandra Sekar

Kevin Kashefi

Andy Fu

Dipankar Pramanik

Sung Hyun Jo

Michael Konevecki

Usha Raghuram

Xiying Chen

Monica Sawkar Mathur

Christopher John Petti

Scott Brad Herner

Federico Nardi

Frank Greer

Mohamed M Hilali

Huiwen Xu

Venkat Ananthan

Dat Nguyen

A method for forming a resistive switching device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring structure is formed overlying the first dielectric material. The method forms one or more first structure comprising a junction material overlying the first wiring structure. A second structure comprising a stack of material is formed overlying the first structure. The second structure includes a resistive switching material, an active conductive material overlying the resistive switching material, and a second wiring material overlying the active conductive material. The second structure is configured such that the resistive switching material is free from a coincident vertical sidewall region with the junction material.

Semiconductor device for a non-volatile (NV) resistive memory and array structure for an array of NV resistive memory

Provided are hybrid electrodes comprising base structures and plugs disposed within the base structures. Also provided are selector elements comprising such hybrid electrodes and memory arrays with selector elements used for addressing individual memory cells. Specifically, the base structure and plug of a hybrid electrode have different compositions but both interface the same dielectric of the selector element. This design allows anti-parallel diode and other configurations with a very few components. The base structure and plug may have different dopants, different stoichiometry of the same alloy, or formed from completely different materials. The interfacing surface portions of a hybrid electrode may have different sizes. A combination of these surface portions (e.g., areas, surface conditions) and materials (e.g., compositions) can be used for tuning operating characteristics of selector elements using such hybrid electrodes.

Current selectors formed using single stack structures

Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichiometric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiO, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.

Sub-oxide interface layer for two-terminal memory

A memory device comprising a doped conductive polycrystalline layer having an electrically resistive portion, is described herein. By way of example, ion implantation to a subset of the conductive polycrystalline layer can degrade and modify the polycrystalline layer, forming the electrically resistive portion. The electrically resistive portion can include resistive switching properties facilitating digital information storage. Parametric control of the ion implantation can facilitate control over corresponding resistive switching properties of the resistive portion. For example, a projected range or depth of the ion implantation can be controlled, allowing for preferential placement of atoms in the resistive portion, and fine-tuning of a forming voltage of the memory device. As another example, dose and number of atoms implanted, type of atoms or ions that are implanted, the conductive polycrystalline material used, and so forth, can facilitate control over switching characteristics of the memory device.

Methods for fabricating resistive memory device switching material using ion implantation

Provided are superconducting circuits and method of forming thereof. A superconducting circuit may include a low loss dielectric (LLD) layer formed from one or both of polycrystalline silicon or polycrystalline germanium. The LLD layer may be formed at a low temperature (e.g., less than about 525&#xb0; C.) using chemical vapor deposition (CVD). Addition of germanium may help to lower the deposition temperature and improve crystallinity of the resulting layer. The LLD layer is formed without adding silicides at the interface of the LLD layer and metal electrode. In some embodiments, an initial layer (e.g., a seed layer or a protective layer) may be formed on a metal electrode prior to forming the LLD layer. For example, the initial layer may include one of zinc sulfide, polycrystalline germanium, or polycrystalline silicon. The initial layer may be deposited at a low pressure (e.g., less than 10 Torr) to ensure higher levels of crystallinity.

Low temperature deposition of low loss dielectric layers in superconducting circuits

Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on a single dielectric layer or on a multilayer dielectric stack.

TiOx based selector element

Scalable RRAM device architecture for a non-volatile memory device and method

Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). A structure including diamond-like carbon (DLC) can be used to surround the semiconductor layer of the MSM stack. The high thermal conductivity of the DLC structure may serve to remove heat from the selector device while higher currents are flowing through the selector element. This may lead to improved reliability and improved endurance.

Diamond like carbon (DLC) as a thermal sink in a selector stack for non-volatile memory application

Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a photo-luminescent or electro-luminescent material. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or combinations thereof.

Photo-induced MSM stack

Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a silicon carbide/silicon nitride nanolaminate stack. The semiconductor layer of the selector element can include a silicon carbon nitride/silicon nitride nanolaminate stack. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or a combination thereof.

SiC&#x2014;Si3N4 nanolaminates as a semiconductor for MSM snapback selector devices

A method of forming a resistive device includes forming a first wiring layer overlying a first dielectric on top of a substrate, forming a junction material, patterning the first wiring layer and junction material to expose a portion of the first dielectric, forming a second dielectric over the patterned first wiring layer, forming an opening in the second dielectric to expose a portion of the junction material, forming a resistive switching material over the portion of the junction material in the opening, the resistive switching material having an intrinsic semiconductor characteristic, forming a conductive material over the resistive switching material, etching the conductive material and the resistive switching material to expose respective sidewalls of the resistive switching material and the conductive material, and the second dielectric, and forming a second wiring layer over the conductive material in contact with the respective sidewalls and the second dielectric.

Device structure for a RRAM and method

A method of forming a non-volatile memory device includes providing a substrate having a surface, depositing a dielectric overlying the surface, forming a first wiring structure overlying the dielectric, depositing silicon material overlying the first wiring structure, the silicon layer having a thickness of less than about 100 Angstroms, depositing silicon germanium material at a temperature raging from about 400 to about 490 Degrees Celsius overlying the first wiring structure using the silicon layer as a seed layer, wherein the silicon germanium material is substantially free of voids and has polycrystalline characteristics, depositing resistive switching material (e.g. amorphous silicon material) overlying the silicon germanium material, depositing a conductive material overlying the resistive material, and forming a second wiring structure overlying the conductive material.

Seed layer for a p+ silicon germanium material for a non-volatile memory device and method

Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can include insulator layers between the semiconductor layer and the metal layers to lower the leakage current of the device. The metal layers of the selector element can include conductive materials such as tungsten, titanium nitride, or combinations thereof.

Tunneling barrier creation in MSM stack as a selector device for non-volatile memory application

Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiO, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.

A method of forming a non-volatile memory device, includes providing a substrate, forming a first dielectric over the substrate, forming a first wiring structure over the first dielectric, forming a first conductor in contact with the first wiring structure, forming a polycrystalline p+ SiGe material over the first conductor at a deposition temperature ranging from about 350 to about 500 Degrees Celsius, forming a polycrystalline silicon conformally over the SiGe material using the SiGe material as a lattice template at a deposition temperature within about 350 to about 500 Degrees Celsius, the polycrystalline silicon having an intrinsic semiconductor characteristic, forming a second conductor over the polycrystalline silicon in physical and electric contact with the resistive polycrystalline silicon, and forming a second wiring structure over the second conductor.

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Santa Clara, CA, United States of America

Mark Harold Clark