Motorola Corporation

Mark G Fernandes

Rajeev Bajaj

Chitra K Subramanian

Olubunmi O Adetutu

James D Hayden

Stanley Michael Filipiak

Hisao Kawasaki

David K Watts

Jeffrey T Wetzel

Subramoney V Iyer

Jaime A Saravia

Archana Redkar

Anthony Mark Miscione

Thom Kobayashi

A method for processing a conductive layer, such as a doped polysilicon layer (14) of a gate stack, provides a degas step after precleaning to reduce particle count and defectivity. The conductive layer is provided on a substrate (10), e.g., a silicon wafer. The substrate (10) and conductive layer are subjected to an elevated temperature, under a vacuum, whereby certain species are liberated. The substrate having the conductive layer formed thereon is then removed from the chamber, and moved to a second, separate chamber, in which a second conductive layer (20) is deposited. By switching chambers, the liberated species are largely prevented from contributing to particle count at the interface between the conductive layers. Alternatively, the second conductive layer is formed in the same chamber, provided that the liberated species are removed from the chamber prior to deposition of the second conductive layer.

Method of processing a conductive layer and forming a semiconductor

A method for polishing a metal layer (20) containing a combination of wide features (12), low density features (14), and high density features (18), is illustrated. A hydrophilic polish pad (24) having a shore D hardness of greater than 50 is used along with slurry (22) containing silica and an acidic based oxidizer such as oxadic acid in a chemical mechanical polishing (CMP) process. The result is less than 5:1 and preferably 1:1. This low selectivity results in the metal layer (20) being polished to a level below the surface of the surrounding oxide in a timed-controlled polish.

Low selectivity chemical mechanical polishing (CMP) process for use on

A semiconductor device has structures to reduced stress notching effects in conductive lines. In one form, the semiconductor device includes a semiconductor die which has a plurality of active conductive lines thereon. The plurality of conductive lines collectively has a first and a second outside edge. In close proximity to each of the first and the second outside edges is a stress reducing line. Each of the stress reducing lines is a non-active structure (in other words does not transmit signals) and functions to reduce stress concentrations on the plurality of active conductive lines which are imposed by overlying insulating and passivation layers. As a result of weakened stress concentrations, the amount of stress notching in the active conductive lines is reduced.

Semiconductor device having structures to reduce stress notching effects

A method for forming a patterned layer of material begins by providing a substrate (12). A device layer (14) is formed overlying the substrate (12). A layer (16) is formed over the device layer (14). Layer (16) is further characterized as being an inorganic dielectric material, such as a plasma enhanced silicon nitride (PEN) material. A mask (18) is positioned adjacent the layer (16). Ultra-violet (UV) light (20) is selectively exposed to the layer (16) through the mask (18). Exposure from the UV light (20) forms exposed regions (16b) and unexposed regions (16a) of the layer (16). The UV light (20) alters an atomic bonding energy of hydrogen atoms within the exposed regions (16b) while not altering unexposed regions (16a). The layer (16) is exposed to an etchant which etches the exposed regions (16b) and unexposed regions (16a) at different rates. The etching forms a patterned layer from the layer ( 16) which may be used as a masking layer.

Method for forming a patterned layer using dielectric materials as a

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Mark G Fernandes