Micron Technology Incorporated

Other

Mark E Jost

Charles H Dennison

Kunal R Parekh

Steven M McDonald

David J Hansen

Bradley J Howard

Zhiping Yin

Mark Fischer

John H Givens

Guy T Blalock

Christophe Pierrat

William Arthur Stanton

Phillip G Wald

Chris W Hill

David S Becker

Erik R Byers

Keith R Cook

Alex J Schrinksy

The present invention relates to methods of forming semiconductor structures. The methods may include disposing electrically conductive material within an opening in a first dielectric material, passivating an upper surface of the electrically conductive material and introducing materials to form an interlayer dielectric upon the passivated upper surface. The present invention also includes methods of passivating surfaces of a semiconductor structure with a nitrogen-containing species.

Methods of forming semiconductor structures

The present invention relates to metallic interconnect having an interlayer dielectric thereover, the metallic interconnect having an upper surface substantially free from oxidation. The metallic interconnect may have an exposed upper surface thereon that is passivated by a nitrogen containing compound.

Interconnect structures with interlayer dielectric

A method for use in fabrication of a semiconductor device comprises forming a conformal conductive layer over a planarized surface of a dielectric layer, and within an opening formed in the dielectric layer. The opening will typically have an aspect ratio of about 4:1 or greater. An etch is performed with specified gasses under a range of specified conditions which removes the conformal conductive layer from the planarized surface, but which leaves unetched the conformal conductive layer within the opening.

Dry etching process to form a conductive layer within an opening without use of a mask during the formation of a semiconductor device

The present invention relates to the formation of an ILD layer while preventing or reducing oxidation of the upper surface of a metallic interconnect. Avoidance of oxidation of the upper surface of a metallic interconnect is achieved according to the present invention by passivating the exposed upper surface of the metallic interconnect prior to formation of the ILD. In order to avoid the oxidation of an upper surface of an interconnect during the formation of an ILD layer, an in situ passivation of the upper surface of the interconnect, immediately prior to or simultaneously with the formation of the ILD layer avoids the problems of the prior art.

Method of forming interconnect structure with interlayer dielectric

A chemical vapor deposition method includes providing a semiconductor substrate within a chemical vapor deposition chamber. At least one liquid deposition precursor is vaporized with a vaporizer to form a flowing vaporized precursor stream. The flowing vaporized precursor stream is initially bypassed from entering the chamber for a first period of time while the substrate is in the deposition chamber. After the first period of time, the flowing vaporized precursor stream is directed to flow into the chamber with the substrate therein under conditions effective to chemical vapor deposit a layer over the substrate. A method of etching a contact opening over a node location on a semiconductor substrate is disclosed.

Methods of etching a contact opening over a node location on a semiconductor substrate

Method of etching a contact opening

As an alternative embodiment and in connection with the reduction of the amount of ammonia in the mixture, processing conditions may be altered from conditions that are less likely to cause formation to oxide husk to conditions that are more likely. For example, processing temperatures sufficient to form passivation layer may be initiated with an ammonia-rich mixture under conditions not likely to cause formation of oxide husk . As the amount of ammonia in the mixture is reduced, processing temperatures may be increased proportionally under conditions that are more likely to cause formation of oxide husk than under conditions previously established when the amount of ammonia in the mixture is greater. The initial formation of some of passivation layer , however, resists the formation of oxide husk . Preferably, the processing temperature will be the same as the deposition temperature for ILD layer

Method of making an electrical device including an interconnect structure

A method of forming structures in semiconductor devices through a buffer or insulator layer comprises the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. This allows for a thinner layer of resist material to be used. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by chemical mechanical planarization.

Utilization of disappearing silicon hard mask for fabrication of semiconductor structures

A method of forming structures in semiconductor devices through a buffer or insulator layer comprises the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by CMP.

Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures

The invention encompasses a method of forming a protective segment of material. A plurality of at least three conductive lines are provided over a semiconductor substrate. A material is formed over the conductive lines, and a patterned masking layer is formed to cover a segment of the material extending between a pair of the conductive lines while leaving another segment of the material uncovered. The uncovered segment of the material is anisotropically etched to form separated spacers from the uncovered segment. The separated spacers are along sidewalls of at least two of the conductive lines. The covered segment of the material remains after the anisotropic etching, and is a protective segment of the material over the semiconductor substrate.

Methods of forming protective segments of material, and etch stops

A semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns. Further, a semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, i) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and ii) while fabricating integrated circuitry elsewhere on the wafer, processing one of the alignment patterns differently from the other to render the one alignment pattern to be different from the other alignment pattern.

Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns

Chemical vapor deposition methods

A method of forming structures in semiconductor devices through a buffer or insulator layer comprising the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. This allows for a thinner layer of resist material to be used. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by chemical mechanical planarization.

A method of forming structures in semiconductor devices through a buffer or insulator layer comprising the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. This allows for a thinner layer of resist material to be used because no additional resist is required to provide a &ldquo;margin of error&rdquo; during the etching to assure the integrity of the barrier layer. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by CMP. A silicon hard mask is difficult to remove by such an abrasive method. However, a silicide material is conducive to abrasive removal. The deposition and annealing of the silicidable material can be a part of the formation of a contact silicide layer at the bottom of a contact opening during the formation of a bitline contact or a capacitor contact.

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Boise, ID, United States of America

Mark E Jost