Freescale Semiconductor,inc.

Nxp Usa, Inc.

Nxp B.v.

Motorola Corporation

Other

Advanced Micro Devices Corporation

Mark Douglas Hall

Mehul D Shroff

Frank Kelsey Baker, Jr

Tushar Praful Merchant

Anirban Roy

Tab Allen Stephens

Michael D Turner

Kurt H Junker

David Russell Tipple

Toni D Van Gompel

Marilyn I Wright

Dharmesh Jawarani

Kyle W Patterson

Douglas M Reber

Edward K Theiss

Srikanteswara Dakshiina-Murthy

Gauri V Karve

Edward Outlaw Travis, Jr

Brian A Winstead

Srikanth Balaji Samavedam

Anis Mahmoud Jarrar

Konstantin V Loiko

Michael P Woo

Rode R Mora

Glenn Charles Abeln

Arkalgud R Sitaram

Chong-Cheng Fu

Mousumi Bhat

Mohamad M Jahanbani

Brian J Fisher

Vikas R Sheth

Olubunmi O Adetutu

Ted R White

Paul Grudowski

Asanga H Perera

John M Grant

Jonathan L Cobb

James Edward Vasek

Jinmiao James Shen

Gregory S Ferguson

Surya Veeraraghavan

Walter J Ciosek

Jin Miao Shen

Steven G H Anderson

Joel Patrick Mitchell

Anadi Srivastava

William D Darlington

Raghaw S Rai

Jesse Yanez

Steven D Frezon

George R Campbell

Robert L Rhoades

Johanes P Suryanata

Craig Allan Cavins

Maryfe Hernandez

An integrated circuit DAC device and fabrication method are provided with a linear bias ladder circuit which generates a plurality of bias voltages, an inverting operational amplifier configured to generate an analog output voltage in response to an input current signal, and a plurality of MMT devices connected between the linear bias ladder circuit and the inverting operational amplifier to implement a DAC with a first current control gate of each MMT device connected to one of the plurality of N different bias voltages, with a second switch control gate of each MMT device connected to receive one of a plurality digital input code values, with a drain terminal of each MMT device connected to a digital bias voltage (Vdbias), and with a source terminal of each MMT device connected to provide the input current signal to the inverting operational amplifier.

DAC and ADC using MMT devices

A semiconductor device and fabrication method are described for forming a nanosheet transistor device by forming a nanosheet transistor stack (-) of alternating Si and SiGe layers which are selectively processed to form metal-containing current terminal or source/drain regions () and to form control terminal electrodes (A-D) which replace the SiGe layers in the nanosheet transistor stack and are positioned between the Si layers which form transistor channel regions in the nanosheet transistor stack to connect the metal source/drain regions, thereby forming a nanosheet transistor device.

Nanosheet transistors with reduced source/drain resistance and associated method of manufacture

A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (--) which are separated from one another by a barrier oxide layer () and which are separately processed to form first remnant silicon germanium nanosheet layers () in the bottom Si/SiGe superlattice structures having a first gate length dimension (DG) and to form second remnant silicon germanium nanosheet layers () in the top Si/SiGe superlattice structures having a second, smaller gate length dimension (DG) so that the nanosheet transistor stack may then be processed to simultaneously form bottom and top gate electrodes which replace, respectively, the first and second remnant silicon germanium nanosheet layers.

Nanosheet device with different gate lengths in same stack

A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (--) which are separated from one another by a barrier oxide layer () and which are separately processed to form bottom gate electrodes having a first gate structure (A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (A-B) in the top Si/SiGe superlattice structures.

Nanosheet transistors with different gate materials in same stack and method of making

A nanosheet semiconductor device and fabrication method are described for integrating the fabrication of nanosheet transistors () and capacitors/sensors () in a single nanosheet process flow by forming separate transistor and capacitor/sensor stacks (A-A,B-B) which are selectively processed to form gate electrode structures (A-C) which replace remnant SiGe sandwich layers in the transistor stack, to form silicon fixed electrodes using silicon nanosheets (C,C) on a first side of the capacitor/sensor stack, and to form SiGe fixed electrodes using SiGe nanosheets (C,C,C) from the middle of remnant SiGe sandwich layers in the capacitor/sensor stack (e.g.,-) which are separated from the silicon fixed electrodes by selectively removing top and bottom SiGe nanosheets (e.g.,--) from the remnant SiGe sandwich layers in the capacitor/sensor stack.

Method of making nanosheet fringe capacitors or MEMS sensors with dissimilar electrode materials

A nanosheet MEMS sensor device and method are described for integrating the fabrication of nanosheet transistors () and MEMS sensors () in a single nanosheet process flow by forming separate nanosheet transistor and MEMS sensor stacks (A-A,B-B) of alternating Si and SiGe layers which are selectively processed to form gate electrodes (A-C) which replace the silicon germanium layers in the nanosheet transistor stack, to form silicon fixed electrodes using silicon layers (B-B-) on a first side of the MEMS sensor stack, and to form silicon cantilever electrodes using silicon layers (B-B-) on a second side of the MEMS sensor stack by forming a narrow trench opening () in the MEMS sensor stack to expose and remove remnant silicon germanium layers on the second side in the MEMS sensor stack.

Nanosheet MEMs sensor device and method of manufacture

A circuit includes a P-channel transistor formed in a P-well and an N-channel transistor formed in an N-well. The first P-channel transistor has a control electrode connected to the P-well. The N-channel transistor is coupled in series with the P-channel transistor and has a control electrode connected to the N-well. Connecting the control electrodes of the P-channel and N-channel transistors to respective P-well and N-well effectively reduces crowbar current in the circuit.

High speed buffer circuit

A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a capacitor or nonvolatile memory cell in a single nanosheet process flow by forming a nanosheet transistor stack (-) of alternating Si and SiGe layers which are selectively processed to form epitaxial source/drain regions (A,B) and to form gate electrodes (A-D) which replace the silicon germanium layers in the nanosheet transistor stack, and then selectively forming one or more insulated conductive electrode layers (e.g.,) adjacent to the nanosheet transistor to define a capacitor or nonvolatile memory cell that is integrated with the nanosheet transistor.

Method of making nanosheet local capacitors and nvm devices

A semiconductor apparatus includes a first device cell and a second device cell. The first device cell includes a first active region including a first set of device fins, an insulator layer disposed over the first set of device fins, a first gate fin over the first set of fins, and a first edge fin disposed over a first edge of the first active region. The second device cell is adjacent the first device cell and includes a second active region including a second set of device fins, the insulator layer disposed over the second set of device fins, a second gate fin over the second set of device fins, and a second edge fin disposed over a second edge of the second active region. The first edge fin and the second edge fin are connected to a power rail, a ground rail, or to each other to define a capacitor between the first device cell and the second device cell.

Decoupling capacitors using regularity finFET structures and methods for making same

A package to die connection system and method are provided. The system includes a semiconductor device having a substrate with a top surface. A gasket is affixed to the top surface of the substrate and has at least one cavity with a portion of the cavity open to a sidewall of the gasket. A semiconductor die is attached to the top surface of the substrate. A sidewall of the semiconductor die is abutted with the sidewall of the gasket. A portion of a metal layer is exposed to the open portion of the cavity. A pillar located in the cavity is electrically connected to the exposed portion of the metal layer.

Package to die connection system and method therefor

An integrated circuit (IC) system includes a substrate, a first doped well of a first polarity in the substrate, a first electrode in contact with the doped well, a buried oxide (BOX) in contact with the doped well in the substrate, a first IC device including a second electrode formed on the BOX, and fuse control circuitry coupled to the first electrode and the second electrode. The fuse control circuitry is configured to cause voltages to be applied to the first and second electrodes to change a resistance level of the BOX in the vicinity of the second electrode.

Antifuses integrated on semiconductor-on-insulator (SOI) substrates

A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

Applications for nanopillar structures

A semiconductor device includes a substrate, first electronic circuitry formed on the substrate, a first diode buried in the substrate under the first electronic circuitry, and a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry.

Semiconductor device with upset event detection and method of making

A method of forming a semiconductor device in an NVM region and in a logic region uses a semiconductor substrate and includes forming a gate region fill material over the NVM region and the logic region. The gate region fill material is patterned over the NVM region to leave a first patterned gate region fill material over the NVM region. An interlayer dielectric is formed around the first patterned gate region fill material. A first portion of the first patterned gate region fill material is removed to form a first opening and leaving a second portion of the first patterned gate region fill material. The first opening is laterally adjacent to the second portion. The first opening is filled with a charge storage layer and a conductive material that includes metal overlying the charge storage layer.

Method for forming a split-gate device

A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.

Systems and methods for reducing power consumption in semiconductor devices

Growing community of inventors

Austin, TX, United States of America

Mark Douglas Hall