Freescale Semiconductor,inc.

Motorola Corporation

Mark DeHerrera

Mark A Durlam

Saied N Tehrani

Eugene Youjun Chen

Jon Michael Slaughter

Nicholas David Rizzo

Kelly Wayne Kyler

Gloria J Kerszykowski

Bradley Neal Engel

Gregory W Grynkewich

Peter K Naji

Clarence J Tracy

Thomas Andre

Joseph J Nahas

Bradley J Garni

Renu Whig Dave

Methods and apparatus are provided for testing a magnetoresistive random access memory (MRAM). A magnetoresistive tunnel junction (MTJ) has a first terminal, a second terminal, and a third terminal. A source measuring unit is coupled to a first terminal of a MTJ to provide DC biasing. A current preamp has an input coupled to a third terminal of the MTJ for receiving current corresponding to a resistance of the MTJ. A pulse generator is AC coupled to the MTJ for programming the MTJ. A method of insitu testing a MTJ in a manufacturing environment uses a probe station coupled to the MTJ. A probe station couples to the MTJ. The MTJ is DC biased for generating a current corresponding to the logic level stored in the MTJ. A pulse for programming the MTJ is AC coupled to the MTJ.

Apparatus for pulse testing a MRAM device and method therefore

An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element () including a first electrode (), a second electrode () and a spacer layer (). The first electrode () and the second electrode () include ferromagnetic layers (&). A spacer layer () is located between the ferromagnetic layer () of the first electrode () and the ferromagnetic layer () of the second electrode () for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers (&). The device includes insulative veils () characterized as electrically isolating the first electrode () and the second electrode (), the insulative veils () including non-magnetic and insulating dielectric properties. Additionally disclosed is a method of fabricating the magnetic element () with insulative veils () that have been transformed from having conductive properties to insulative properties through oxygen plasma ashing techniques.

Magnetic element with insulating veils and fabricating method thereof

An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.

MRAM and methods for reading the MRAM

A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.

Magnetoresistive random access memory device structures and methods for fabricating the same

An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element ( ) including a first electrode ( ), a second electrode ( ) and a spacer layer ( ). The first electrode ( ) and the second electrode ( ) include ferromagnetic layers ( & ). A spacer layer ( ) is located between the ferromagnetic layer ( ) of the first electrode ( ) and the ferromagnetic layer ( ) of the second electrode ( ) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers ( & ). The device includes insulative veils ( ) characterized as electrically isolating the first electrode ( ) and the second electrode ( ), the insulative veils ( ) including non-magnetic and insulating dielectric properties. Additionally disclosed is a method of fabricating the magnetic element ( ) with insulative veils ( ) that have been transformed from having conductive properties to insulative properties through oxygen plasma ashing techniques.

Method of fabricating a magnetic element with insulating veils

Magnetoresistive random access memory device structures

An MTJ cell including an insulator layer of material between magnetic material layers with the insulator layer of material having a greater attraction for a third material than the magnetic material layers. The third material is introduced to one or both so that when the cell is heated the third material is redistributed from the magnetic material layer to the insulator layer. Upon redistribution the insulator layer becomes an insulator layer material. Also, a first diffusion barrier layer is positioned between a first metal electrode and one of the magnetic material layers and/or a second diffusion barrier layer is positioned between a second metal electrode and the other magnetic material layer to prevent diffusion of the metal in the electrodes into the magnetic material layers.

Method of fabricating thermally stable MTJ cell and apparatus

A magneto-electronic component includes an electrically conductive layer for generating a magnetic field, a ferromagnetic cladding layer adjacent to the electrically conductive layer, and an antiferromagnetic layer adjacent to the ferromagnetic cladding layer.

Magnetic random access memory having digit lines and bit lines with a ferromagnetic cladding layer

A method of fabricating an MRAM cell includes providing an isolation transistor on a semiconductor substrate and forming an interconnect stack on the substrate in communication with one terminal of the transistor. A via is formed on the upper end of the stack so as to extend from a position below the digit line to a position above the digit line. The via also extends above the upper surface of a dielectric layer to provide an alignment key. A MTJ memory cell is positioned on the upper surface in contact with the via, and the ends of a free layer of magnetic material are spaced from the ends of a pinned edge of magnetic material by using sidewall spacers and selective etching.

High density MRAM cell array

Magnetic tunnel junction random access memory architecture in which an array of memory cells is arranged in rows and columns and each memory cell includes a magnetic tunnel junction and a control transistor connected in parallel. A control line is connected to the gate of each control transistor in a row of control transistors and a metal programming line extending adjacent to each magnetic tunnel junction is connected to the control line in spaced apart intervals by vias. Further, groups of memory cells in each column are connected in series to form local bit lines which are connected in parallel to global bit lines. The series-parallel configuration is read using a centrally located column to provide a reference signal and data from columns on each side of the reference column is compared to the reference signal or two columns in proximity are differentially compared.

MTJ MRAM series-parallel architecture

An improved and novel magnetic element (,) including a plurality of thin film layers wherein the bit end magneto-static demagnetizing fields cancel the total positive coupling of the structure to obtain dual magnetic states in a zero external field. Additionally disclosed is a method of fabricating a magnetic element (,) by providing a plurality of thin film layers wherein the bit end magneto-static demagnetizing fields of the thin film layers cancel the total positive coupling of the structure to obtain dual magnetic states in a zero external field.

Growing community of inventors

Tempe, AZ, United States of America

Mark DeHerrera