Intel Corporation

Sony Group Corporation

Sony Corporation

Mark Armstrong

Tahir Ghani

Kelin J Kuhn

Seiyon Kim

Willy Rachmady

Anand S Murthy

Biswajeet Guha

Cory E Weber

Scott E Thompson

Thomas Hoffmann

Bernhard Sell

Leonard P Guler

William Hsu

Christopher P Auth

Han Wui Then

Mark T Bohr

Rafael Rios

Abhijit Jayant Pethe

Paul A Packan

Giuseppe Curello

Akm A Ahsan

Guannan Liu

Stephen M Cea

Harold W Kennel

Aaron D Lilak

Gerhard Schrom

Swaminathan Sivakumar

Sing-Chung Hu

Bruce E Beattie

Hyung-Jin Lee

Ayan Kar

Jun Sung Kang

Sunit Tyagi

Saurabh Morarka

Max Wei

M Reaz Shaheed

Rui Ma

Wilfred Gomes

Fatih Hamzaoglu

Travis W LaJoie

Pei-Hua Wang

Chieh-Jen Ku

Kaizad Rumy Mistry

Kalyan C Kolluru

Juan G Alzate-Vinasco

Nicholas A Thomson

Chris Auth

Pulkit Jain

Qiang Yu

Carlos Nieva-Lozano

Hyuk Ju Ryu

Said Rami

James D Waldemer

Sameer Jayanta Joglekar

Sayan Saha

Keith c/o Intel Corporation Zawadzki

A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Integration methods to fabricate internal spacers for nanowire devices

A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

Decoupling capacitors and methods of fabrication

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

Planar buried channel structure integrated with non-planar structures

Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

Integrated nanowire and nanoribbon patterning in transistor manufacture

An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.

FinFET varactor quality factor improvement

Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

FIN shaping using templates and integrated circuit structures resulting therefrom

Buried channel structure integrated with non-planar structures

A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

Self-aligned nanowire

Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

Field-effect transistors with asymmetric gate stacks

Fin shaping using templates and integrated circuit structures resulting therefrom

A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.

Dual mode snap back circuit device

Growing community of inventors

Portland, OR, United States of America

Mark Armstrong