Texas Instruments Corporation

Mark Allen Gerber

Kurt Peter Wachtler

Abram M Castro

David N Walter

Duy-Loan T Le

Wyatt Allen Huddleston

Shawn Martin O'Conner

A semiconductor device () comprising a leadframe () having an assembly pad () in a first horizontal plane (), the pad's first surface () with a semiconductor chip () attached; further a plurality of leads () in a parallel second horizontal plane () offset from the first plane in the direction of the attached chip, the leads having a third surface () with bonding wires, and an opposite fourth surface (); a package () encapsulating leadframe, chip, and wires, the package having a fifth surface () parallel to the first and second planes; a plurality of recess holes () in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder () filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

Semiconductor package with lead frame and recessed solder terminals

A semiconductor device has a semiconductor chip having a first surface with metallized terminals and a parallel second surface. A frame of insulating material adheres to at the sidewalls of the chip. The frame has a first surface planar with the first chip surface and a parallel second surface planar with the second chip surface. The first frame surface includes one or more embedded metallic fiducials extending from the first surface to the insulating material. At least one film of sputtered metal extends from the terminals across the surface of the polymeric layer to the fiducials. The film is patterned to form extended contact pads over the frame and rerouting traces between the chip terminals and the extended contact pads. The film adheres to the surfaces.

Packaged semiconductor devices

A method for fabricating packaged semiconductor devices; attaching a batch-sized metallic grid with openings onto an adhesive tape having an insulating clear core covered by a layer of UV-releasable adhesive, the openings sized larger than a semiconductor chip; attaching a semiconductor chip onto the tape of each window, the chip terminals facing the adhesive surface; laminating insulating material of low coefficient of thermal expansion to fill gaps between each chip and respective grid; turning over assembly to place a carrier under backside of chips and lamination and to remove the tape; plasma-cleaning the assembly front side and sputtering uniform at least one metal layer across the assembly; optionally plating metal layers; and patterning the metal layers to form rerouting traces and extended contact pads for assembly.

Method and structure of packaging semiconductor devices

A circuit assembly includes a substrate having a substrate electrical circuit, opposite top and bottom substrate surfaces, and a substrate hole extending through the substrate. The circuit assembly also includes a discrete component assembly electrically connected to the substrate electrical circuit and a support member attached to the discrete component. At least a portion of the discrete component is physically mounted in the substrate hole.

Circuit assembly

A semiconductor chip () assembled on a substrate (). The substrate has a first surface () including conductive traces (), which have a first length () and a first width (), the first width being uniform along the first length, and further a pitch () to respective adjacent traces. The semiconductor chip has a second surface () including contact pads (); the second surface faces the first surface spaced apart by a gap (). A conductive pillar () contacts each contact pad; the pillar includes a metal core () and a solder body (), which connects the core to the respective trace across the gap. The pillar core () has an oblong cross section of a second width () and a second length () greater than the second width. Trace pitch () is equal to or smaller than twice the second width (). The trace pitch is equal to or smaller than the second length ().

Semiconductor flip-chip system having oblong connectors and reduced trace pitches

An improved semiconductor device package is manufactured by attaching semiconductor chips () on an insulating substrate () having contact pads (). A mold is provided, which has a top portion () with metal protrusions () at locations matching the pad locations. The protrusions are shaped as truncated cones. The substrate and the chips are loaded onto the bottom mold portion (); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions approach the contact pads. Encapsulation compound is introduced into the cavity and the protrusions create apertures through the encapsulation compound towards the pad locations.

Method for fabricating array-molded package-on-package

A process flow exposing and cleaning contact surfaces employing a liquid cleaning agent such as flux to penetrate the interface between the glassy coats and the surface of metal and to delaminate the coats from the metal, and then, at elevated temperatures, to use the agent's vapor pressure to break up the glassy coats into smaller pieces. The glassy coats are prevented by their low density to penetrate into the molten solder. Finally, at ambient temperature, the floating filler debris is water-washed and rinsed away. Cleaning agents include low-viscosity liquids (oils) and flux, which do not decompose at elevated temperatures and are mixed with components operable to provide, at the elevated temperatures, the fumes for sufficient vapor pressure to break up and dislodge the coats from the metal contacts.

Method for exposing and cleaning insulating coats from metal contact surfaces

A semiconductor device with a sheet-like insulating substrate () integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads () in pad locations has an encapsulated region on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures () at the pad locations for external communication with the pad metal surfaces. The apertures may have not-smooth sidewall surfaces and may be filled with solder material () to contact the pads. Metal-filled surface grooves () in the encapsulated region, with smooth groove bottom and sidewalls, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly.

Array-molded package-on-package having redistribution lines

A semiconductor system () of one or more semiconductor interposers () with a certain dimension (), conductive vias () extending from the first to the second surface, with terminals and attached non-reflow metal studs () at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips () have a dimension () narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate () has terminals and reflow bodies () to connect to the studs of the projecting interposer.

Packaged system of semiconductor chips having a semiconductor interposer

Array molded package-on-package having redistribution lines

Attaching a semiconductor chip to a substrate by applying mechanical vibrations () to a polymeric compound () and the contacting areas () of a first () and a second () metallic member immersed in the compound, while the two metallic members approach () each other until they touch. The mechanical vibration causes displacements of the first member relative to the second member, and the vibration includes displacements () oriented at right angles to the direction () of the approach. The polymeric compound () includes a non-conductive adhesive resin paste (NCP) and filler particles; the paste is deposited before the attaching step. The first member () is affixed to the chip and the second member () to the substrate.

Method for fine-pitch, low stress flip-chip interconnect

A device has a first semiconductor chip () with contact pads in an interior first set () and a peripheral second set (). A deformed sphere () of non-reflow metal such as gold is placed on each contact pad of the first and second sets. At least one additional deformed sphere () is placed on the first set pads, forming column-shaped spacers. The first chip is attached to a substrate () with a chip attachment location and a third set of contact pads () near the location. Low profile bond wires () span between the pads of the third set and the second set. A second semiconductor chip () of a size has a fourth set of contact pads () at locations matching the first set pads. The second chip is placed over the first chip so that the fourth set pads are aligned with the spacers on the matching first set pads, and at least one edge of the second chip overhangs the sphere on at least one pad of the second set. A reflow metal () bonds the spacers to the second chip, while the spacers space the first and second chips by a gap () wide enough for placing the wire spans to the second set pads.

Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices

Disclosed are methods and devices for providing improved semiconductor packages and POP IC assemblies using the improved packages with reduced warping. According to disclosed embodiments of the inventions, a packaged semiconductor device for use in a POP assembly includes an encapsulated region generally defined by the substrate surface. The encapsulant is provided with contact apertures permitting external communication with contacts on the substrate and coupled to an encapsulated chip. Preferred embodiments of the invention are described in which the contact aperture sidewalls are angled within the range of approximately 10-30 degrees or more from vertical and in which the contact aperture is provided a gas release channel to permit gas to escape during reflow.

Package-on-package semiconductor assembly

A method, comprising bonding a first wire to a single die bond pad to form a first bond, bonding the first wire to a bond post to form a second bond, bonding a second wire to the first bond, and coupling the second wire to the bond post.

Growing community of inventors

Lucas, TX, United States of America

Mark Allen Gerber