Texas Instruments Corporation

Mark A Kressley

Arthur M Wilson

Luigi Colombo

Mark R Visokay

Rajesh B Khamankar

Kenneth G Vickers

Guoqiang Xing

James M Drumm

Juanita G Miller

Moody K Forgey

Dean L Frew

Philip E Hecker, Jr

Chi-Cheong Shen

Akitoshi Nishimura

Daniel A Baudouin

Adin E Hyslop

Randall E Johnson

Jeffrey W Janzen

Rick Elder

John E Finklea

John E Hanicak

A ceramic header configured to form a portion of an electronic device package includes a mounting portion configured to provide a mounting surface for an electronic device. In addition, the ceramic header includes one or more conductive input-output connectors operable to provide electrical connections from a first surface of the ceramic header to a second surface of the ceramic header. The ceramic header also includes one or more thermally polished surfaces.

Method for packaging a microelectromechanical system (MEMS) device

Ceramic header method

An electrode structure for a capacitor. The electrode structure includes a contact plug comprising an oxidation barrier and a bottom electrode comprising a conductive adhesion-promoting portion and an oxidation-resistant portion , the adhesion-promoting portion contacting the oxidation barrier of the contact plug. In further embodiments, the oxidation barrier and adhesion-promoting portion comprise Ti&mdash;Al&mdash;N.

Integrated circuit capacitor and memory

A semiconductor device is disclosed. The device includes an integrated circuit chip having integral de-coupling capacitors on the chip backside. The de-coupling capacitors includes a metal layer in intimate contact with the semiconductor substrate of the integrated circuit, a dielectric layer and a second metal layer. The second metal layer is segmented to form multiple capacitors, and each capacitor is interconnected to power supplies of the chip. Interconnection to different integrated circuit packages is provided. A method of making the semiconductor device is also disclosed.

Integrated capacitor on the back of a chip

A method of making a microelectronic circuit and the connection pattern therefor including the steps of providing a substrate (3), preferably silicon and preferably including a layer of nickel (38) under a layer of gold (36) thereon. Regions are formed on the substrate for connection of electrical components to the substrate using a first metallurgy, preferably gold and a pattern of bumps (5, 7) is formed of a second metallurgy different from the first metallurgy, preferably lead/tin solder. An interconnection pattern is formed on the substrate contacting at least one bump and at least one pad. The pattern of solder bumps is formed by providing a coupon (31) and patterning the bumps on the coupon and applied to the substrate while attached to the coupon, then heated to cause flow of the bumps onto the substrate. The coupon is then removed from the bumps with the bumps remaining on the substrate. Electrical components are applied to the region of first metallurgy and electrically bonded by wire bonding or Tape Automated Bonding techniques. Electrical components are applied to the region of the second metallurgy and electrically bonded by flip-chip technique.

Solder bump transfer for microelectronics packaging and assembly

A method of fabricating an anode plate 40 having a multiplicity of grooves 50 for use in a field emission flat panel display device comprises the steps of providing a transparent planar substrate 42 having a plurality of electrically conductive, parallel stripes 46 comprising the anode electrode of the device; etching a plurality of grooves 50 in the surface of the substrate in the spaces between the stripes 46; and then applying phosphor material 48.sub.R, 48.sub.G and 48.sub.B over the stripes 46. In one embodiment, a plurality of grooves 50', having generally vertical sidewalls, are formed in the upper surface of planar substrate 42' at the interstices of conductors 46. In a second embodiment, a plurality of grooves 50', having generally curved sidewalls, are formed in the upper surface of planar substrate 42' at the interstices of conductors 46'. In a third embodiment, a plurality of grooves 50', having generally vertical sidewalls, are formed in the upper surface of an insulating material 52 located between conductors 46'. In a fourth embodiment, a plurality of grooves 50'', having generally curved sidewalls, are formed in the upper surface of an insulating material 52' between conductors 46''. In a fifth embodiment, a plurality of grooves are formed in the upper surface of planar substrate 100, and insulating material 108 is applied over the grooves. In a sixth embodiment, a plurality of grooves are formed in both the surface of the planar substrate 120 and the surface of insulating material 128.

Method for fabricating a field emission device anode plate having

The multi-chip circuit module of the invention comprises a plurality of circuit chips assembled in a laminated stack. Each chip includes a plurality of layers of thin film interconnect patterns in the normal configuration, except for the final layer or layers, which comprise a reroute pattern that locates all circuit input and output pads along a single edge of each chip. The relocated pads are provided with contact bumps to facilitate the addition of a bonded lead to each I/O pad extending therefrom to a point beyond the edge of each chip. Thus, upon lamination the protruding tips form an array of leads on a single lateral face of the laminated chip stack.

Three dimensional assembly of integrated circuit chips

Growing community of inventors

Richardson, TX, United States of America

Mark A Kressley