Freescale Semiconductor,inc.

Motorola Corporation

Other

Marius K Orlowski

Chun-Li Liu

James David Burnett

Bich-Yen Nguyen

Matthew W Stoker

Mariam G Sadaka

Ted R White

Olubunmi O Adetutu

Sinan Goktepeli

Voon-Yew Thean

Alexander Barr

Peter L G Ventzek

Alexander L Barr

Vance H Adams

Suresh Venkatesan

Tushar Praful Merchant

Shahid Rauf

Leo Mathew

Philip J Tobin

Brian A Winstead

Alexander Hoefler

Shawn George Thomas

Ko-Min Chang

Tab Allen Stephens

Carlos A Mazure

Shih K Cheng

Karl Wimmer

Ramachandran Muralidhar

James D Hayden

Craig T Swift

William James Taylor, Jr

Jon T Fitch

Frank Kelsey Baker, Jr

Rajesh A Rao

Keith E Witek

Kuo-Tung Chang

Dharmesh Jawarani

Kurt H Junker

Christopher C Hobbs

Omar Zia

Shih-Wei Sun

David Gilmer

John M Grant

Alexander A Demkov

Victor H Vartanian

Choh-Fei Yeap

Brian J Goolsby

Prasad V Alluri

Yasuhito Shiho

Mark C Foisy

Michael Rendon

Jack Higman

Jim Hayden

Phillip J Stout

Iuval R Clejan

Matthew S Noell

Shiang-Chyong Luo

Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region. A contact extends into the first current electrode region and is electrically coupled to the first current electrode region.

Transistors with immersed contacts

Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region.

A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.

Single transistor memory cell with reduced recombination rates

A method includes forming a semiconductor structure, the semiconductor structure includes a first current electrode region, a second current electrode region, and a channel region, the channel region is located between the first current electrode region and the second current electrode region, wherein the channel region is located in a fin structure of the semiconductor structure, wherein a carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region. The method further includes forming a first contact, wherein forming the first contact includes removing a first portion of the semiconductor structure to form an opening, wherein the opening is in the first current electrode region and forming contact material in the opening.

Transistor with immersed contacts and methods of forming thereof

An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher Vlying between a portion associated with a relatively lower Vand the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher Vof the channel region. A process for forming the electronic device is also disclosed.

Process for forming an electronic device including a fin-type transistor structure

An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.

Process of forming an electronic device including a layer of discontinuous storage elements

Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.

Transistor devices with nano-crystal gate structures

A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region () is formed over a substrate that is bi-axially stressed. Source () and drain () regions are formed over the substrate. The source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region. The uni-axial stress and the bi-axially stress are both compressive for P-channel transistors and tensile for N-channel transistors. Both transistor types can be included on the same integrated circuit.

Method and apparatus for mobility enhancement in a semiconductor device

A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack () formed over a substrate (), thereby forming an etched gate () having a vertical sidewall profile (). By constructing the gate stack () with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile () may be obtained.

Method to control the gate sidewall profile by graded material composition

Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

Semiconductor device structure

A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portion of the dielectric layer and the sacrificial layer which is located between two columns of metallic catalysts. The lateral opening includes a neck portion and a cavity portion which is used as a constrained space to grow a nanotube. A plasma is used to apply electric charge that forms an electric field which controls the direction of formation of the nanotubes. Nanotubes from each column of metallic catalyst are laterally grown and either abut or merge into one nanotube. Contact to the nanotube may be made from either the neck portion or the columns of metallic catalysts.

Laterally grown nanotubes and method of formation

Electronic device including a fin-type transistor structure and a process for forming the electronic device

Methods and apparatus are provided for non-volatile semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises, a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can also be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.

MOS device with nano-crystal gate structure

An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor.

MOS devices with multi-layer gate stack

A non-planar semiconductor device () starts with a silicon fin (). A source of germanium (e.g.) is provided to the fin (). Some embodiments may use deposition to provide germanium; some embodiments may use ion implantation () to provide germanium; other methods may also be used to provide germanium. The fin () is then oxidized to form a silicon germanium channel region in the fin (). In some embodiments, the entire fin () is transformed from silicon to silicon germanium. One or more fins () may be used to form a non-planar semiconductor device, such as, for example, a FINFET, MIGFET, Tri-gate transistor, or multi-gate transistor.

Method for forming a semiconductor device and structure thereof

Growing community of inventors

Austin, TX, United States of America

Marius K Orlowski