Lsi Logic Corporation

Lsi Corporation

Mario Garza

Keith K Chao

Nicholas K Eib

John V Jensen

Paul G Filseth

Ranko L Scepanovic

Nicholas F Pasch

Edwin R Jones

Richard D Schinella

Dusan Petranovic

Lav D Ivanovic

Neal Patrick Callan

Ebo H Croffie

Christopher L Neville

Kunal N Taravade

Ramnath Venkatraman

Emery O Sugasawara

George Edward Bailey

Colin D Yates

Travis Brist

Philip Eric Jackson

Olga A Kobozeva

The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.

Process window compliant corrections of design layout

A method and system of optimizing the illumination of a mask in a photolithography process. A specific, preferred method includes the steps of: loading minimum design rules of a layout, loading exposure latitude constraints, loading mask error constraints, loading initial illumination conditions, simulating current illumination conditions, obtaining dose-to-print threshold from the minimum design rules (i.e., lines-and-space feature), applying OPC on the layout using the dose-to-print threshold, calculating DOF using the exposure latitude and mask error constraints, changing the illumination conditions in order to attempt to maximize common DOF with the exposure latitude and mask error constraints, and continuing the process until maximum common DOF is obtained.

OPC based illumination optimization with mask error constraints

A method and system for detecting defects in a physical mask used for fabricating a semiconductor device having multiple layers is disclosed, where each layer has a corresponding mask. The method and system include receiving a digital image of the mask, and automatically detecting edges of the mask in the image using pattern recognition. The detected edges, which are stored in a standard format, are imported along with processing parameters into a process simulator that generates an estimated aerial image of the silicon layout that would be produced by a scanner using the mask and the parameters. The estimated aerial image is then compared to an intended aerial image of the same layer, and any differences found that are greater than predefined tolerances are determined to horizontal defects. In addition, effects that the horizontal defects may have on adjacent layers are analyzed to discover vertical defects.

Mask defect analysis for both horizontal and vertical processing effects

A method of silicon design reproducibility enhancement using priority assignments prior to performing a conventional optical proximity correction process on a device. The present invention seeks to improve the manufacturability of VLSI devices. The present invention inserts a priority assignment step prior to the conventional OPC correction process in order to assert better control over transistor parameters. The priority assignment step sorts the layout by degree of importance to the cell/device performance. Areas designated as critical are given higher priority values while areas designated as non-critical are given lower priority values. The present invention imposes more precise accuracy requirements to high priority value areas and less precise accuracy requirements to low priority value areas. As a result, the present invention imposes the tightest accuracy requirements to critical areas of device performance, rather than attempting to achieve overall accuracy during the OPC correction process.

Optical proximity correction method using weighted priorities

A method and system is provided for automatically calibrating a masking process simulator using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected. Data defining the calibration mask and at least one of the process parameters are input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The alim image and the detected edges of the digital image are then overlaid, and a distance between contours of the pattern in the alim image and the detected edges is measured. One or more mathematical algorithms are used to iteratively change the values of the processing parameters until a set of processing parameter values are found that produces a minimum distance between the contours of the pattern in the alim image and the detected edges.

Automatic calibration of a masking process simulator

An improved process simulation system for simulating results of fabrication process for a semiconductor device design is disclosed. According to the method and system disclosed herein, the process simulator receives processing parameters and mask data for at least two masks as input, and simulates results of the fabrication process such that an aerial image is generated for each layer of the device that was simulated. After generating the aerial images, the process simulator superimposes the aerial images to create a composite image. An operator is then allowed to misalign at least one of the images in relation to the other images based on one or more offset values. The composite image showing the misalignment is then displayed, allowing the operator to view nominal process capability as well as process fluctuations prior to fabrication of the semiconductor device.

Wafer process critical dimension, alignment, and registration analysis simulation tool

A method and system for automatically calibrating a masking process simulator using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected. Data defining the calibration mask and the process parameters are input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The alim image and the detected edges of the digital image are then overlaid, and a distance between contours of the pattern in the alim image and the detected edges is measured. One or more mathematical algorithms are used to iteratively change the values of the processing parameters until a set of processing parameter values are found that produces a minimum distance between the contours of the pattern in the alim image and the detected edges.

A method for adjusting preliminary feature position characteristics of a preliminary mask pattern on a mask to produce a desired etch pattern on a substrate having desired feature position characteristics.

Optical and etch proximity correction

A mask is designed for use in a photolithographic process to offset effects of light diffraction. At least one region having a length along each edge of a mask feature is defined. Error values at selected points on the mask are derived from an aerial image of the mask features and a target light intensity measured during IC fabrication process development. A matrix is derived representing the contributions of light amplitude due to movement of each region in a direction normal to the region. The amount of movement of each region is based on least-squares fitting the linear expressions in the matrix to the error values. The amount of movement may be adjusted for movement of an adjacent region.

Mask correction optimization

The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.

Method and apparatus for application of proximity correction with relative segmentation

The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment without taking into consideration the other segments of the piece.

Method and apparatus for application of proximity correction with unitary segmentation

Disclosed is a pupil aperture, and method for making the pupil aperture for use in a photolithography scanner system. The pupil aperture includes a plate having a set of pole apertures that are radially offset from a reference center point of the plate. The plate further includes a horizontal reference line that intersects the reference center point. The horizontal reference line is used to define a target angle that is between about 15 degrees and about 35 degrees from the horizontal reference line. The target angle defines an off-axis location for each of the set of pole apertures. In a specific aspect of this invention, a set ranging between 3 to 9 pole apertures can be defined in the plate, and their offset from the center point can be selected to be between about 0.3 inches and about 0.9 inches.

Off-axis pupil aperture and method for making the same

A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design rule checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.

Performing optical proximity correction with the aid of design rule checkers

Disclosed is a method for correcting a layout design using a design rule checker. The method includes providing a layout design file having the layout design that is to be corrected for optical proximity by the design rule checker. Providing a run set to the design rule checker. The run set includes a plurality of correction values that are used to correct a plurality of features of the layout design that have a selected space dimension. Identifying each of the plurality of features that have the selected space dimension. The method further includes correcting each of the plurality of features that have the selected space dimension with one correction value of the plurality of correction values of the run set. Preferably, the run set is generated from a correction table that has the plurality of correction values.

Optical proximity correction method and apparatus

The present invention is a method and apparatus for systematically applying proximity corrections to a mask pattern, wherein the pattern is divided into a grid of equally sized grid rectangles, an inner rectangle comprising a plurality of grid rectangles is formed, an outer rectangle comprising a second plurality of grid rectangles and the inner rectangle is formed and proximity correction is applied to the pattern contained within the inner rectangle as a function of the pattern contained within the outer rectangle.

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Sunnyvale, CA, United States of America

Mario Garza