International Business Machines Corporation

Tokyo Electron Limited

Marinus J P Hopstaken

Takashi Ando

Effendi Leobandung

Vijay Narayanan

Kevin K Chan

Jeehwan Kim

Eduard Albert Cartier

Kandabara N Tapily

Talia S Gershon

Deborah A Neumayer

Yun Seog Lee

Dae-Gyu Park

Paul Charles Jamison

Masaharu Kobayashi

Cory Wajda

Young-Hee Kim

Uzma B Rana

Steven Consiglio

Tsong-Lin Tai

Takaaki Tsunomura

Devendra K Sadana

Stephen W Bedell

Joel Pereira De Souza

John Albrecht Ott

Kam-Leung Lee

John C Collins

John Bruley

A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing Hgas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.

Method for controlling the forming voltage in resistive random access memory devices

A method for fabricating a photovoltaic device includes forming a polycrystalline absorber layer including Cu&#x2014;Zn&#x2014;Sn&#x2014;S(Se) (CZTSSe) over a substrate. The absorber layer is rapid thermal annealed in a sealed chamber having elemental sulfur within the chamber. A sulfur content profile is graded in the absorber layer in accordance with a size of the elemental sulfur and an anneal temperature to provide a graduated bandgap profile for the absorber layer. Additional layers are formed on the absorber layer to complete the photovoltaic device.

Bandgap grading of CZTS solar cell

An anode structure for rechargeable lithium-ion batteries that have a high-capacity are provided. The anode structure, which is made utilizing an anodic etching process, is of unitary construction and includes a non-porous region and a porous region including a top porous layer (Porous Region) having a first thickness and a first porosity, and a bottom porous layer (Porous Region) located beneath the top porous layer and forming an interface with the non-porous region. At least an upper portion of the non-porous region and the entirety of the porous region are composed of silicon, and the bottom porous layer has a second thickness that is greater than the first thickness, and a second porosity that is greater than the first porosity.

Method of making an anode structure containing a porous region

Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shallow, abrupt and highly activated tin (Sn) extension implant junction. The method includes forming a semiconductor fin on a substrate. A gate is formed over a channel region of the semiconductor fin. A Sn extension implant junction is formed on a surface of the semiconductor fin in the channel region.

Shallow, abrupt and highly activated tin extension implant junction

An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Selective dopant junction for a group III-V semiconductor device

An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Growing community of inventors

Carmel, NY, United States of America

Marinus J P Hopstaken