Chippac, Inc.

Stats Chippac Pte. Ltd.

Hewlett-packard Company

Varian Associates, Inc.

Marcos Karnezos

Flynn P Carson

Taekeun Lee

Youngcheol Kim

Seng Guan Chow

Il Kwon Shim

Rajendra D Pendse

Byung Joon Han

Kambhampati Ramakrishna

Hyeog Chan Kwon

Armand P Neukermans

Jong Wook Ju

Koo Hong Lee

Kyung-Moon Kim

Sang Ho Lee

Orion K Starr

Walter A Bush, Jr

Yong-Bae Kim

Howard H Nakanos

Randal S Jones

Moon Hee Lee

A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces as appropriate for interconnection with the die (on the die attach side) and with other elements (such as other packages in a multi-package module). Interconnection with a die is made by wire bonding to exposed traces on a die attach side of the metal layer, and bond fingers and lands for access to testing the package are provided on the opposite (land) side of the metal layer.

Semiconductor multi-package module including tape substrate land grid array package stacked over ball grid array package

A module having multiple die includes a first die on a first substrate and an inverted second package stacked over the first die, with, where necessary, provision is made for a standoff between the second package and the first die. Also, methods for making the module include steps of providing a first package having a first die attached onto an upward facing side of a first package substrate, and stacking an inverted second package over the die on the first package, provision being made where necessary for a standoff between the second package and the first package die to avoid damaging impact between the downward-facing side of the second package and wire bonds connecting the first die to the first package substrate.

Multiple chip package module having inverted package stacked over die

Adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device in a stacked semiconductor assembly, include a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate or so that the die attach side of the upper package faces away from the lower die or lower package substrate.

Adhesive/spacer island structure for stacking over wire bonded die

A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces as appropriate for interconnection with the die and with other elements. Interconnection with a die is made by wire bonding to exposed traces on a die attach side of the metal layer, and bond fingers and lands for access to testing the package are provided on the land side of the metal layer.

A method for making a semiconductor multi-package module includes; providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages

A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.

Plastic ball grid array package with integral heatsink

Stacked semiconductor assemblies in which a first die is mounted active side upward on a first substrate and is electrically interconnected to the substrate by wire bonding; an adhesive/spacer structure is formed upon the active side of the first die; and a device such as a die or a package or a heat spreader, having an electrically nonconductive side, is mounted upon the adhesive/spacer structure with the electrically nonconductive side facing the first wire bonded die. The side of the device facing the first wire bonded die may be made electrically nonconductive by having an electrically insulating layer, such as a dielectric film adhesive. Also, methods for making the assemblies are disclosed.

Stacked semiconductor package having adhesive/spacer structure and insulation

A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-up flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.

Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages

An integrated circuit package system includes: a substrate; a first device attached to the substrate; a shield attached to the substrate and surrounding the first device; apertures formed within the shield; the shield configured to block electromagnetic energy that passes through the apertures; and an encapsulation material deposited through the apertures.

Integrated circuit package system including shield

A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.

Method for making semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package

A method for making a semiconductor multi-package module includes a processor and a plurality of memory packages mounted on a surface of the multipackage module substrate. In some embodiments the memory packages include stacked die packages, and in some embodiments the memory packages include stacked memory packages. In some embodiments the processor is situated at or near the center of the multipackage module substrate and the plurality of memory packages or of stacked memory package assemblies are situated on the multipackage module substrate adjacent the processor.

Method of fabricating a semiconductor multipackage module including a processor and memory package assemblies

Methods for forming flip chip interconnection, in which the bump interconnect is defined at least in part by an underfill. The underfill includes a material that is thermally cured; that is, raising the temperature of the underfill material can result in progressive curing of the underfill through stages including a gel stage and a fully cured stage. According to the invention, during at least an early stage in the process the semiconductor chip is carried by a thermode, which is employed to control the temperature of the assembly in a specified way. Also, flip chip interconnections and flip chip packages made according to the methods of invention.

Flip chip interconnection

A method of manufacture of an integrated circuit package system which includes providing a substrate and attaching a first device to the substrate. Attaching a shield to the substrate. Processing the shield to form apertures and configuring the shield to block electromagnetic energy that passes through the apertures.

A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.

Growing community of inventors

Palo Alto, CA, United States of America

Marcos Karnezos